diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 53 |
1 files changed, 37 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index e5af96d2..cffc56d1 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -453,26 +453,46 @@ static bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num) | |||
453 | return valid; | 453 | return valid; |
454 | } | 454 | } |
455 | 455 | ||
456 | static void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g, | 456 | /* Following are the blocks of registers that the ucode |
457 | u32 *num_sm_dsm_perf_regs, | 457 | stores in the extended region.*/ |
458 | u32 **sm_dsm_perf_regs, | 458 | /* == ctxsw_extended_sm_dsm_perf_counter_register_stride_v() ? */ |
459 | u32 *perf_register_stride) | 459 | static const u32 _num_sm_dsm_perf_regs; |
460 | /* == ctxsw_extended_sm_dsm_perf_counter_control_register_stride_v() ?*/ | ||
461 | static const u32 _num_sm_dsm_perf_ctrl_regs = 2; | ||
462 | static u32 *_sm_dsm_perf_regs; | ||
463 | static u32 _sm_dsm_perf_ctrl_regs[2]; | ||
464 | |||
465 | void gr_gm20b_init_sm_dsm_reg_info(void) | ||
460 | { | 466 | { |
461 | gr_gk20a_get_sm_dsm_perf_regs(g, num_sm_dsm_perf_regs, | 467 | if (_sm_dsm_perf_ctrl_regs[0] != 0) |
462 | sm_dsm_perf_regs, | 468 | return; |
463 | perf_register_stride); | 469 | |
464 | *perf_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_register_stride_v(); | 470 | _sm_dsm_perf_ctrl_regs[0] = |
471 | gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control0_r(); | ||
472 | _sm_dsm_perf_ctrl_regs[1] = | ||
473 | gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(); | ||
465 | } | 474 | } |
466 | 475 | ||
467 | static void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, | 476 | void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g, |
468 | u32 *num_sm_dsm_perf_regs, | 477 | u32 *num_sm_dsm_perf_regs, |
469 | u32 **sm_dsm_perf_regs, | 478 | u32 **sm_dsm_perf_regs, |
470 | u32 *ctrl_register_stride) | 479 | u32 *perf_register_stride) |
471 | { | 480 | { |
472 | gr_gk20a_get_sm_dsm_perf_ctrl_regs(g, num_sm_dsm_perf_regs, | 481 | *num_sm_dsm_perf_regs = _num_sm_dsm_perf_regs; |
473 | sm_dsm_perf_regs, | 482 | *sm_dsm_perf_regs = _sm_dsm_perf_regs; |
474 | ctrl_register_stride); | 483 | *perf_register_stride = 0; |
475 | *ctrl_register_stride = ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); | 484 | } |
485 | |||
486 | void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, | ||
487 | u32 *num_sm_dsm_perf_ctrl_regs, | ||
488 | u32 **sm_dsm_perf_ctrl_regs, | ||
489 | u32 *ctrl_register_stride) | ||
490 | { | ||
491 | *num_sm_dsm_perf_ctrl_regs = _num_sm_dsm_perf_ctrl_regs; | ||
492 | *sm_dsm_perf_ctrl_regs = _sm_dsm_perf_ctrl_regs; | ||
493 | |||
494 | *ctrl_register_stride = | ||
495 | ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); | ||
476 | } | 496 | } |
477 | 497 | ||
478 | static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 498 | static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
@@ -1072,4 +1092,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1072 | gops->gr.get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc; | 1092 | gops->gr.get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc; |
1073 | gops->gr.get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask; | 1093 | gops->gr.get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask; |
1074 | gops->gr.get_max_fbps_count = gr_gm20b_get_max_fbps_count; | 1094 | gops->gr.get_max_fbps_count = gr_gm20b_get_max_fbps_count; |
1095 | gops->gr.init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info; | ||
1075 | } | 1096 | } |