diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 5 |
2 files changed, 9 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index e30ca96f..5133fb35 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -180,6 +180,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
180 | struct gpu_ops *gops = &g->ops; | 180 | struct gpu_ops *gops = &g->ops; |
181 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; | 181 | struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; |
182 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | 182 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); |
183 | u32 val; | ||
183 | 184 | ||
184 | *gops = gm20b_ops; | 185 | *gops = gm20b_ops; |
185 | gops->securegpccs = false; | 186 | gops->securegpccs = false; |
@@ -187,8 +188,8 @@ int gm20b_init_hal(struct gk20a *g) | |||
187 | if (platform->is_fmodel) { | 188 | if (platform->is_fmodel) { |
188 | gops->privsecurity = 1; | 189 | gops->privsecurity = 1; |
189 | } else { | 190 | } else { |
190 | if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0) & | 191 | tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0, &val); |
191 | PRIV_SECURITY_DISABLE) { | 192 | if (val & PRIV_SECURITY_DISABLE) { |
192 | gk20a_dbg_info("priv security is disabled in HW"); | 193 | gk20a_dbg_info("priv security is disabled in HW"); |
193 | gops->privsecurity = 0; | 194 | gops->privsecurity = 0; |
194 | } else { | 195 | } else { |
@@ -200,8 +201,8 @@ int gm20b_init_hal(struct gk20a *g) | |||
200 | gk20a_dbg_info("running ASIM with PRIV security disabled"); | 201 | gk20a_dbg_info("running ASIM with PRIV security disabled"); |
201 | gops->privsecurity = 0; | 202 | gops->privsecurity = 0; |
202 | } else { | 203 | } else { |
203 | if (tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0) & | 204 | tegra_fuse_readl(FUSE_OPT_PRIV_SEC_DIS_0, &val); |
204 | PRIV_SECURITY_DISABLE) { | 205 | if (val & PRIV_SECURITY_DISABLE) { |
205 | gops->privsecurity = 0; | 206 | gops->privsecurity = 0; |
206 | } else { | 207 | } else { |
207 | gk20a_dbg_info("priv security is not supported but enabled"); | 208 | gk20a_dbg_info("priv security is not supported but enabled"); |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 30e8fa67..5c5a889a 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -256,12 +256,15 @@ void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr) | |||
256 | /*Dump Security related fuses*/ | 256 | /*Dump Security related fuses*/ |
257 | static void pmu_dump_security_fuses_gm20b(struct gk20a *g) | 257 | static void pmu_dump_security_fuses_gm20b(struct gk20a *g) |
258 | { | 258 | { |
259 | u32 val; | ||
260 | |||
259 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", | 261 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", |
260 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); | 262 | gk20a_readl(g, fuse_opt_sec_debug_en_r())); |
261 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", | 263 | gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", |
262 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); | 264 | gk20a_readl(g, fuse_opt_priv_sec_en_r())); |
265 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); | ||
263 | gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", | 266 | gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", |
264 | tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0)); | 267 | val); |
265 | } | 268 | } |
266 | 269 | ||
267 | void gm20b_init_pmu_ops(struct gpu_ops *gops) | 270 | void gm20b_init_pmu_ops(struct gpu_ops *gops) |