diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 121 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.h | 10 |
2 files changed, 125 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index 791cc45b..e4e385fb 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -26,7 +26,7 @@ | |||
26 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> | 26 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> |
27 | #include <nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h> | 27 | #include <nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h> |
28 | 28 | ||
29 | #include "gk20a/ltc_common.c" | 29 | #include "gk20a/ltc_gk20a.h" |
30 | #include "ltc_gm20b.h" | 30 | #include "ltc_gm20b.h" |
31 | 31 | ||
32 | static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | 32 | static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) |
@@ -349,13 +349,124 @@ static int gm20b_determine_L2_size_bytes(struct gk20a *g) | |||
349 | return cache_size; | 349 | return cache_size; |
350 | } | 350 | } |
351 | 351 | ||
352 | /* | ||
353 | * Sets the ZBC color for the passed index. | ||
354 | */ | ||
355 | void gm20b_ltc_set_zbc_color_entry(struct gk20a *g, | ||
356 | struct zbc_entry *color_val, | ||
357 | u32 index) | ||
358 | { | ||
359 | u32 i; | ||
360 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; | ||
361 | |||
362 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | ||
363 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | ||
364 | |||
365 | for (i = 0; | ||
366 | i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) { | ||
367 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i), | ||
368 | color_val->color_l2[i]); | ||
369 | } | ||
370 | gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); | ||
371 | } | ||
372 | |||
373 | /* | ||
374 | * Sets the ZBC depth for the passed index. | ||
375 | */ | ||
376 | void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g, | ||
377 | struct zbc_entry *depth_val, | ||
378 | u32 index) | ||
379 | { | ||
380 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; | ||
381 | |||
382 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | ||
383 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | ||
384 | |||
385 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), | ||
386 | depth_val->depth); | ||
387 | |||
388 | gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); | ||
389 | } | ||
390 | |||
391 | void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) | ||
392 | { | ||
393 | u32 max_size = gr->max_comptag_mem; | ||
394 | u32 max_comptag_lines = max_size << 3; | ||
395 | |||
396 | u32 compbit_base_post_divide; | ||
397 | u64 compbit_base_post_multiply64; | ||
398 | u64 compbit_store_iova; | ||
399 | u64 compbit_base_post_divide64; | ||
400 | |||
401 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) | ||
402 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); | ||
403 | else | ||
404 | compbit_store_iova = g->ops.mm.get_iova_addr(g, | ||
405 | gr->compbit_store.mem.priv.sgt->sgl, 0); | ||
406 | |||
407 | compbit_base_post_divide64 = compbit_store_iova >> | ||
408 | ltc_ltcs_ltss_cbc_base_alignment_shift_v(); | ||
409 | |||
410 | do_div(compbit_base_post_divide64, g->ltc_count); | ||
411 | compbit_base_post_divide = u64_lo32(compbit_base_post_divide64); | ||
412 | |||
413 | compbit_base_post_multiply64 = ((u64)compbit_base_post_divide * | ||
414 | g->ltc_count) << ltc_ltcs_ltss_cbc_base_alignment_shift_v(); | ||
415 | |||
416 | if (compbit_base_post_multiply64 < compbit_store_iova) | ||
417 | compbit_base_post_divide++; | ||
418 | |||
419 | /* Bug 1477079 indicates sw adjustment on the posted divided base. */ | ||
420 | if (g->ops.ltc.cbc_fix_config) | ||
421 | compbit_base_post_divide = | ||
422 | g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide); | ||
423 | |||
424 | gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(), | ||
425 | compbit_base_post_divide); | ||
426 | |||
427 | gk20a_dbg(gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte, | ||
428 | "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n", | ||
429 | (u32)(compbit_store_iova >> 32), | ||
430 | (u32)(compbit_store_iova & 0xffffffff), | ||
431 | compbit_base_post_divide); | ||
432 | |||
433 | gr->compbit_store.base_hw = compbit_base_post_divide; | ||
434 | |||
435 | g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate, | ||
436 | 0, max_comptag_lines - 1); | ||
437 | |||
438 | } | ||
439 | |||
440 | #ifdef CONFIG_DEBUG_FS | ||
441 | static void gm20b_ltc_sync_debugfs(struct gk20a *g) | ||
442 | { | ||
443 | u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); | ||
444 | |||
445 | nvgpu_spinlock_acquire(&g->debugfs_lock); | ||
446 | if (g->mm.ltc_enabled != g->mm.ltc_enabled_debug) { | ||
447 | u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); | ||
448 | |||
449 | if (g->mm.ltc_enabled_debug) | ||
450 | /* bypass disabled (normal caching ops)*/ | ||
451 | reg &= ~reg_f; | ||
452 | else | ||
453 | /* bypass enabled (no caching) */ | ||
454 | reg |= reg_f; | ||
455 | |||
456 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); | ||
457 | g->mm.ltc_enabled = g->mm.ltc_enabled_debug; | ||
458 | } | ||
459 | nvgpu_spinlock_release(&g->debugfs_lock); | ||
460 | } | ||
461 | #endif | ||
462 | |||
352 | void gm20b_init_ltc(struct gpu_ops *gops) | 463 | void gm20b_init_ltc(struct gpu_ops *gops) |
353 | { | 464 | { |
354 | /* Gk20a reused ops. */ | 465 | /* Gk20a reused ops. */ |
355 | gops->ltc.determine_L2_size_bytes = gm20b_determine_L2_size_bytes; | 466 | gops->ltc.determine_L2_size_bytes = gm20b_determine_L2_size_bytes; |
356 | gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry; | 467 | gops->ltc.set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry; |
357 | gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry; | 468 | gops->ltc.set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry; |
358 | gops->ltc.init_cbc = gk20a_ltc_init_cbc; | 469 | gops->ltc.init_cbc = gm20b_ltc_init_cbc; |
359 | 470 | ||
360 | /* GM20b specific ops. */ | 471 | /* GM20b specific ops. */ |
361 | gops->ltc.init_fs_state = gm20b_ltc_init_fs_state; | 472 | gops->ltc.init_fs_state = gm20b_ltc_init_fs_state; |
@@ -365,6 +476,6 @@ void gm20b_init_ltc(struct gpu_ops *gops) | |||
365 | gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; | 476 | gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; |
366 | gops->ltc.flush = gm20b_flush_ltc; | 477 | gops->ltc.flush = gm20b_flush_ltc; |
367 | #ifdef CONFIG_DEBUG_FS | 478 | #ifdef CONFIG_DEBUG_FS |
368 | gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; | 479 | gops->ltc.sync_debugfs = gm20b_ltc_sync_debugfs; |
369 | #endif | 480 | #endif |
370 | } | 481 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h index fcd263de..4fe83250 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B L2 | 2 | * GM20B L2 |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -17,6 +17,14 @@ | |||
17 | #define _NVHOST_GM20B_LTC | 17 | #define _NVHOST_GM20B_LTC |
18 | struct gpu_ops; | 18 | struct gpu_ops; |
19 | 19 | ||
20 | void gm20b_ltc_set_zbc_color_entry(struct gk20a *g, | ||
21 | struct zbc_entry *color_val, | ||
22 | u32 index); | ||
23 | void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g, | ||
24 | struct zbc_entry *depth_val, | ||
25 | u32 index); | ||
26 | void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr); | ||
27 | |||
20 | void gm20b_init_ltc(struct gpu_ops *gops); | 28 | void gm20b_init_ltc(struct gpu_ops *gops); |
21 | void gm20b_ltc_init_fs_state(struct gk20a *g); | 29 | void gm20b_ltc_init_fs_state(struct gk20a *g); |
22 | int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | 30 | int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, |