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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c3
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c5
-rw-r--r--drivers/gpu/nvgpu/gm20b/ltc_gm20b.c3
3 files changed, 4 insertions, 7 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 7400a9e4..717e5487 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -725,11 +725,10 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
725 u32 reg_offset = gr_gpcs_gpccs_falcon_hwcfg_r() - 725 u32 reg_offset = gr_gpcs_gpccs_falcon_hwcfg_r() -
726 gr_fecs_falcon_hwcfg_r(); 726 gr_fecs_falcon_hwcfg_r();
727 u8 falcon_id_mask = 0; 727 u8 falcon_id_mask = 0;
728 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
729 728
730 gk20a_dbg_fn(""); 729 gk20a_dbg_fn("");
731 730
732 if (platform->is_fmodel) { 731 if (g->is_fmodel) {
733 gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7), 732 gk20a_writel(g, gr_fecs_ctxsw_mailbox_r(7),
734 gr_fecs_ctxsw_mailbox_value_f(0xc0de7777)); 733 gr_fecs_ctxsw_mailbox_value_f(0xc0de7777));
735 gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7), 734 gk20a_writel(g, gr_gpccs_ctxsw_mailbox_r(7),
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 24acf29c..c190a83c 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -183,14 +183,13 @@ int gm20b_init_hal(struct gk20a *g)
183{ 183{
184 struct gpu_ops *gops = &g->ops; 184 struct gpu_ops *gops = &g->ops;
185 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics; 185 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
186 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
187 u32 val; 186 u32 val;
188 187
189 gops->clock_gating = gm20b_ops.clock_gating; 188 gops->clock_gating = gm20b_ops.clock_gating;
190 gops->securegpccs = false; 189 gops->securegpccs = false;
191 gops->pmupstate = false; 190 gops->pmupstate = false;
192#ifdef CONFIG_TEGRA_ACR 191#ifdef CONFIG_TEGRA_ACR
193 if (platform->is_fmodel) { 192 if (g->is_fmodel) {
194 gops->privsecurity = 1; 193 gops->privsecurity = 1;
195 } else { 194 } else {
196 val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); 195 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
@@ -202,7 +201,7 @@ int gm20b_init_hal(struct gk20a *g)
202 } 201 }
203 } 202 }
204#else 203#else
205 if (platform->is_fmodel) { 204 if (g->is_fmodel) {
206 gk20a_dbg_info("running ASIM with PRIV security disabled"); 205 gk20a_dbg_info("running ASIM with PRIV security disabled");
207 gops->privsecurity = 0; 206 gops->privsecurity = 0;
208 } else { 207 } else {
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
index 17882e72..90504e52 100644
--- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
@@ -49,7 +49,6 @@ static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
49 u32 compbit_backing_size; 49 u32 compbit_backing_size;
50 50
51 int err; 51 int err;
52 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
53 52
54 gk20a_dbg_fn(""); 53 gk20a_dbg_fn("");
55 54
@@ -82,7 +81,7 @@ static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
82 gk20a_dbg_info("max comptag lines : %d", 81 gk20a_dbg_info("max comptag lines : %d",
83 max_comptag_lines); 82 max_comptag_lines);
84 83
85 if (platform->is_fmodel) 84 if (g->is_fmodel)
86 err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size); 85 err = gk20a_ltc_alloc_phys_cbc(g, compbit_backing_size);
87 else 86 else
88 err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size); 87 err = gk20a_ltc_alloc_virt_cbc(g, compbit_backing_size);