diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 71 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 66 |
3 files changed, 79 insertions, 70 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 19782412..afdfba91 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -28,7 +28,7 @@ | |||
28 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> | 28 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> |
29 | #include <nvgpu/hw/gm20b/hw_pbdma_gm20b.h> | 29 | #include <nvgpu/hw/gm20b/hw_pbdma_gm20b.h> |
30 | 30 | ||
31 | static void channel_gm20b_bind(struct channel_gk20a *c) | 31 | void channel_gm20b_bind(struct channel_gk20a *c) |
32 | { | 32 | { |
33 | struct gk20a *g = c->g; | 33 | struct gk20a *g = c->g; |
34 | 34 | ||
@@ -69,7 +69,7 @@ static inline u32 gm20b_engine_id_to_mmu_id(struct gk20a *g, u32 engine_id) | |||
69 | return fault_id; | 69 | return fault_id; |
70 | } | 70 | } |
71 | 71 | ||
72 | static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | 72 | void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, |
73 | unsigned long engine_ids) | 73 | unsigned long engine_ids) |
74 | { | 74 | { |
75 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; | 75 | unsigned long delay = GR_IDLE_CHECK_DEFAULT; |
@@ -113,12 +113,12 @@ static void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | |||
113 | gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0); | 113 | gk20a_writel(g, fifo_trigger_mmu_fault_r(engine_id), 0); |
114 | } | 114 | } |
115 | 115 | ||
116 | static u32 gm20b_fifo_get_num_fifos(struct gk20a *g) | 116 | u32 gm20b_fifo_get_num_fifos(struct gk20a *g) |
117 | { | 117 | { |
118 | return ccsr_channel__size_1_v(); | 118 | return ccsr_channel__size_1_v(); |
119 | } | 119 | } |
120 | 120 | ||
121 | static void gm20b_device_info_data_parse(struct gk20a *g, | 121 | void gm20b_device_info_data_parse(struct gk20a *g, |
122 | u32 table_entry, u32 *inst_id, | 122 | u32 table_entry, u32 *inst_id, |
123 | u32 *pri_base, u32 *fault_id) | 123 | u32 *pri_base, u32 *fault_id) |
124 | { | 124 | { |
@@ -139,7 +139,7 @@ static void gm20b_device_info_data_parse(struct gk20a *g, | |||
139 | top_device_info_data_type_v(table_entry)); | 139 | top_device_info_data_type_v(table_entry)); |
140 | } | 140 | } |
141 | 141 | ||
142 | static void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) | 142 | void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) |
143 | { | 143 | { |
144 | /* | 144 | /* |
145 | * These are all errors which indicate something really wrong | 145 | * These are all errors which indicate something really wrong |
@@ -182,64 +182,3 @@ static void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) | |||
182 | f->intr.pbdma.restartable_0 = | 182 | f->intr.pbdma.restartable_0 = |
183 | pbdma_intr_0_device_pending_f(); | 183 | pbdma_intr_0_device_pending_f(); |
184 | } | 184 | } |
185 | |||
186 | void gm20b_init_fifo(struct gpu_ops *gops) | ||
187 | { | ||
188 | gops->fifo.init_fifo_setup_hw = gk20a_init_fifo_setup_hw; | ||
189 | gops->fifo.bind_channel = channel_gm20b_bind; | ||
190 | gops->fifo.unbind_channel = gk20a_fifo_channel_unbind; | ||
191 | gops->fifo.disable_channel = gk20a_fifo_disable_channel; | ||
192 | gops->fifo.enable_channel = gk20a_fifo_enable_channel; | ||
193 | gops->fifo.alloc_inst = gk20a_fifo_alloc_inst; | ||
194 | gops->fifo.free_inst = gk20a_fifo_free_inst; | ||
195 | gops->fifo.setup_ramfc = gk20a_fifo_setup_ramfc; | ||
196 | gops->fifo.channel_set_priority = gk20a_fifo_set_priority; | ||
197 | gops->fifo.channel_set_timeslice = gk20a_fifo_set_timeslice; | ||
198 | gops->fifo.default_timeslice_us = gk20a_fifo_default_timeslice_us; | ||
199 | gops->fifo.setup_userd = gk20a_fifo_setup_userd; | ||
200 | gops->fifo.userd_gp_get = gk20a_fifo_userd_gp_get; | ||
201 | gops->fifo.userd_gp_put = gk20a_fifo_userd_gp_put; | ||
202 | gops->fifo.userd_pb_get = gk20a_fifo_userd_pb_get; | ||
203 | gops->fifo.pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val; | ||
204 | |||
205 | gops->fifo.preempt_channel = gk20a_fifo_preempt_channel; | ||
206 | gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg; | ||
207 | gops->fifo.update_runlist = gk20a_fifo_update_runlist; | ||
208 | gops->fifo.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault; | ||
209 | gops->fifo.get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info; | ||
210 | gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; | ||
211 | gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos; | ||
212 | gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature; | ||
213 | gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave; | ||
214 | gops->fifo.tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice; | ||
215 | gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch; | ||
216 | gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type; | ||
217 | gops->fifo.device_info_data_parse = gm20b_device_info_data_parse; | ||
218 | gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; | ||
219 | gops->fifo.init_engine_info = gk20a_fifo_init_engine_info; | ||
220 | gops->fifo.runlist_entry_size = ram_rl_entry_size_v; | ||
221 | gops->fifo.get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry; | ||
222 | gops->fifo.get_ch_runlist_entry = gk20a_get_ch_runlist_entry; | ||
223 | gops->fifo.is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc; | ||
224 | gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; | ||
225 | gops->fifo.dump_eng_status = gk20a_dump_eng_status; | ||
226 | gops->fifo.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc; | ||
227 | gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask; | ||
228 | gops->fifo.is_preempt_pending = gk20a_fifo_is_preempt_pending; | ||
229 | gops->fifo.init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs; | ||
230 | gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw; | ||
231 | gops->fifo.teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg; | ||
232 | gops->fifo.handle_sched_error = gk20a_fifo_handle_sched_error; | ||
233 | gops->fifo.handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0; | ||
234 | gops->fifo.handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1; | ||
235 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
236 | gops->fifo.alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf; | ||
237 | gops->fifo.free_syncpt_buf = gk20a_fifo_free_syncpt_buf; | ||
238 | gops->fifo.add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd; | ||
239 | gops->fifo.get_syncpt_wait_cmd_size = | ||
240 | gk20a_fifo_get_syncpt_wait_cmd_size; | ||
241 | gops->fifo.add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd; | ||
242 | gops->fifo.get_syncpt_incr_cmd_size = | ||
243 | gk20a_fifo_get_syncpt_incr_cmd_size; | ||
244 | #endif | ||
245 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h index ca452d21..1b1b8cc1 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Fifo | 2 | * GM20B Fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -17,5 +17,13 @@ | |||
17 | #define _NVHOST_GM20B_FIFO | 17 | #define _NVHOST_GM20B_FIFO |
18 | struct gk20a; | 18 | struct gk20a; |
19 | 19 | ||
20 | void gm20b_init_fifo(struct gpu_ops *gops); | 20 | void channel_gm20b_bind(struct channel_gk20a *c); |
21 | void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | ||
22 | unsigned long engine_ids); | ||
23 | u32 gm20b_fifo_get_num_fifos(struct gk20a *g); | ||
24 | void gm20b_device_info_data_parse(struct gk20a *g, | ||
25 | u32 table_entry, u32 *inst_id, | ||
26 | u32 *pri_base, u32 *fault_id); | ||
27 | void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); | ||
28 | |||
21 | #endif | 29 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 87acb25c..bdee1149 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -15,6 +15,7 @@ | |||
15 | 15 | ||
16 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
17 | #include "gk20a/dbg_gpu_gk20a.h" | 17 | #include "gk20a/dbg_gpu_gk20a.h" |
18 | #include "gk20a/fifo_gk20a.h" | ||
18 | #include "gk20a/css_gr_gk20a.h" | 19 | #include "gk20a/css_gr_gk20a.h" |
19 | #include "gk20a/mc_gk20a.h" | 20 | #include "gk20a/mc_gk20a.h" |
20 | #include "gk20a/bus_gk20a.h" | 21 | #include "gk20a/bus_gk20a.h" |
@@ -46,6 +47,9 @@ | |||
46 | 47 | ||
47 | #include <nvgpu/hw/gm20b/hw_proj_gm20b.h> | 48 | #include <nvgpu/hw/gm20b/hw_proj_gm20b.h> |
48 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | 49 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> |
50 | #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h> | ||
51 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> | ||
52 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> | ||
49 | 53 | ||
50 | #define PRIV_SECURITY_DISABLE 0x01 | 54 | #define PRIV_SECURITY_DISABLE 0x01 |
51 | 55 | ||
@@ -202,6 +206,64 @@ static const struct gpu_ops gm20b_ops = { | |||
202 | .pg_gr_load_gating_prod = | 206 | .pg_gr_load_gating_prod = |
203 | gr_gm20b_pg_gr_load_gating_prod, | 207 | gr_gm20b_pg_gr_load_gating_prod, |
204 | }, | 208 | }, |
209 | .fifo = { | ||
210 | .init_fifo_setup_hw = gk20a_init_fifo_setup_hw, | ||
211 | .bind_channel = channel_gm20b_bind, | ||
212 | .unbind_channel = gk20a_fifo_channel_unbind, | ||
213 | .disable_channel = gk20a_fifo_disable_channel, | ||
214 | .enable_channel = gk20a_fifo_enable_channel, | ||
215 | .alloc_inst = gk20a_fifo_alloc_inst, | ||
216 | .free_inst = gk20a_fifo_free_inst, | ||
217 | .setup_ramfc = gk20a_fifo_setup_ramfc, | ||
218 | .channel_set_priority = gk20a_fifo_set_priority, | ||
219 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
220 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | ||
221 | .setup_userd = gk20a_fifo_setup_userd, | ||
222 | .userd_gp_get = gk20a_fifo_userd_gp_get, | ||
223 | .userd_gp_put = gk20a_fifo_userd_gp_put, | ||
224 | .userd_pb_get = gk20a_fifo_userd_pb_get, | ||
225 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | ||
226 | .preempt_channel = gk20a_fifo_preempt_channel, | ||
227 | .preempt_tsg = gk20a_fifo_preempt_tsg, | ||
228 | .update_runlist = gk20a_fifo_update_runlist, | ||
229 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | ||
230 | .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info, | ||
231 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | ||
232 | .get_num_fifos = gm20b_fifo_get_num_fifos, | ||
233 | .get_pbdma_signature = gk20a_fifo_get_pbdma_signature, | ||
234 | .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, | ||
235 | .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, | ||
236 | .force_reset_ch = gk20a_fifo_force_reset_ch, | ||
237 | .engine_enum_from_type = gk20a_fifo_engine_enum_from_type, | ||
238 | .device_info_data_parse = gm20b_device_info_data_parse, | ||
239 | .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, | ||
240 | .init_engine_info = gk20a_fifo_init_engine_info, | ||
241 | .runlist_entry_size = ram_rl_entry_size_v, | ||
242 | .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, | ||
243 | .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, | ||
244 | .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, | ||
245 | .dump_pbdma_status = gk20a_dump_pbdma_status, | ||
246 | .dump_eng_status = gk20a_dump_eng_status, | ||
247 | .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, | ||
248 | .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, | ||
249 | .is_preempt_pending = gk20a_fifo_is_preempt_pending, | ||
250 | .init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs, | ||
251 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | ||
252 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, | ||
253 | .handle_sched_error = gk20a_fifo_handle_sched_error, | ||
254 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, | ||
255 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, | ||
256 | .tsg_bind_channel = gk20a_tsg_bind_channel, | ||
257 | .tsg_unbind_channel = gk20a_tsg_unbind_channel, | ||
258 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
259 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | ||
260 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | ||
261 | .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, | ||
262 | .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, | ||
263 | .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, | ||
264 | .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, | ||
265 | #endif | ||
266 | }, | ||
205 | .mc = { | 267 | .mc = { |
206 | .intr_enable = mc_gk20a_intr_enable, | 268 | .intr_enable = mc_gk20a_intr_enable, |
207 | .intr_unit_config = mc_gk20a_intr_unit_config, | 269 | .intr_unit_config = mc_gk20a_intr_unit_config, |
@@ -271,6 +333,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
271 | 333 | ||
272 | gops->ltc = gm20b_ops.ltc; | 334 | gops->ltc = gm20b_ops.ltc; |
273 | gops->clock_gating = gm20b_ops.clock_gating; | 335 | gops->clock_gating = gm20b_ops.clock_gating; |
336 | gops->fifo = gm20b_ops.fifo; | ||
274 | gops->mc = gm20b_ops.mc; | 337 | gops->mc = gm20b_ops.mc; |
275 | gops->dbg_session_ops = gm20b_ops.dbg_session_ops; | 338 | gops->dbg_session_ops = gm20b_ops.dbg_session_ops; |
276 | gops->debug = gm20b_ops.debug; | 339 | gops->debug = gm20b_ops.debug; |
@@ -320,7 +383,6 @@ int gm20b_init_hal(struct gk20a *g) | |||
320 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 383 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
321 | gm20b_init_gr(gops); | 384 | gm20b_init_gr(gops); |
322 | gm20b_init_fb(gops); | 385 | gm20b_init_fb(gops); |
323 | gm20b_init_fifo(gops); | ||
324 | gm20b_init_ce2(gops); | 386 | gm20b_init_ce2(gops); |
325 | gm20b_init_gr_ctx(gops); | 387 | gm20b_init_gr_ctx(gops); |
326 | gm20b_init_mm(gops); | 388 | gm20b_init_mm(gops); |
@@ -328,7 +390,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
328 | gm20b_init_clk_ops(gops); | 390 | gm20b_init_clk_ops(gops); |
329 | gm20b_init_regops(gops); | 391 | gm20b_init_regops(gops); |
330 | gm20b_init_therm_ops(gops); | 392 | gm20b_init_therm_ops(gops); |
331 | gk20a_init_tsg_ops(gops); | 393 | |
332 | g->name = "gm20b"; | 394 | g->name = "gm20b"; |
333 | 395 | ||
334 | c->twod_class = FERMI_TWOD_A; | 396 | c->twod_class = FERMI_TWOD_A; |