diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index e4691588..7f0e3055 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Clocks | 2 | * GM20B Clocks |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -1135,16 +1135,19 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1135 | if (!gk20a_clk_get(g)) | 1135 | if (!gk20a_clk_get(g)) |
1136 | return -EINVAL; | 1136 | return -EINVAL; |
1137 | 1137 | ||
1138 | c = clk->tegra_clk; | ||
1139 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1140 | /* | 1138 | /* |
1141 | * On Tegra GPU clock exposed to frequency governor is a shared user on | 1139 | * On Tegra GPU clock exposed to frequency governor is a shared user on |
1142 | * GPCPLL bus (gbus). The latter can be accessed as GPU clock parent. | 1140 | * GPCPLL bus (gbus). The latter can be accessed as GPU clock parent. |
1143 | * Respectively the grandparent is PLL reference clock. | 1141 | * Respectively the grandparent is PLL reference clock. |
1144 | */ | 1142 | */ |
1145 | c = clk_get_parent(c); | 1143 | c = clk_get_parent(clk->tegra_clk); |
1144 | |||
1145 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1146 | ref = clk_get_parent(clk_get_parent(c)); | ||
1147 | #elif defined (CONFIG_COMMON_CLK) | ||
1148 | ref = clk_get_sys("gpu_ref", "gpu_ref"); | ||
1146 | #endif | 1149 | #endif |
1147 | ref = clk_get_parent(c); | 1150 | |
1148 | if (IS_ERR(ref)) { | 1151 | if (IS_ERR(ref)) { |
1149 | gk20a_err(dev_from_gk20a(g), | 1152 | gk20a_err(dev_from_gk20a(g), |
1150 | "failed to get GPCPLL reference clock"); | 1153 | "failed to get GPCPLL reference clock"); |
@@ -1297,6 +1300,11 @@ int gm20b_register_gpcclk(struct gk20a *g) { | |||
1297 | struct clk_gk20a *clk = &g->clk; | 1300 | struct clk_gk20a *clk = &g->clk; |
1298 | struct clk_init_data init; | 1301 | struct clk_init_data init; |
1299 | struct clk *c; | 1302 | struct clk *c; |
1303 | int err = 0; | ||
1304 | |||
1305 | err = gm20b_init_clk_setup_sw(g); | ||
1306 | if (err) | ||
1307 | return err; | ||
1300 | 1308 | ||
1301 | init.name = "gpcclk"; | 1309 | init.name = "gpcclk"; |
1302 | init.ops = &gk20a_clk_ops; | 1310 | init.ops = &gk20a_clk_ops; |
@@ -1313,10 +1321,11 @@ int gm20b_register_gpcclk(struct gk20a *g) { | |||
1313 | return -EINVAL; | 1321 | return -EINVAL; |
1314 | } | 1322 | } |
1315 | 1323 | ||
1324 | clk->g = g; | ||
1316 | clk->tegra_clk = c; | 1325 | clk->tegra_clk = c; |
1317 | clk_register_clkdev(c, "gpcclk", "gpcclk"); | 1326 | clk_register_clkdev(c, "gpcclk", "gpcclk"); |
1318 | 1327 | ||
1319 | return 0; | 1328 | return err; |
1320 | } | 1329 | } |
1321 | #endif /* CONFIG_COMMON_CLK */ | 1330 | #endif /* CONFIG_COMMON_CLK */ |
1322 | 1331 | ||
@@ -1520,15 +1529,16 @@ static int gm20b_init_clk_support(struct gk20a *g) | |||
1520 | 1529 | ||
1521 | gk20a_dbg_fn(""); | 1530 | gk20a_dbg_fn(""); |
1522 | 1531 | ||
1523 | clk->g = g; | ||
1524 | |||
1525 | err = gm20b_init_clk_reset_enable_hw(g); | 1532 | err = gm20b_init_clk_reset_enable_hw(g); |
1526 | if (err) | 1533 | if (err) |
1527 | return err; | 1534 | return err; |
1528 | 1535 | ||
1536 | #ifdef CONFIG_TEGRA_CLK_FRAMEWORK | ||
1537 | clk->g = g; | ||
1529 | err = gm20b_init_clk_setup_sw(g); | 1538 | err = gm20b_init_clk_setup_sw(g); |
1530 | if (err) | 1539 | if (err) |
1531 | return err; | 1540 | return err; |
1541 | #endif | ||
1532 | 1542 | ||
1533 | mutex_lock(&clk->clk_mutex); | 1543 | mutex_lock(&clk->clk_mutex); |
1534 | clk->clk_hw_on = true; | 1544 | clk->clk_hw_on = true; |