4 files changed, 89 insertions, 35 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/bus_gm20b.c b/drivers/gpu/nvgpu/gm20b/bus_gm20b.c
new file mode 100644
index 00000000..68a4b15f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm20b/bus_gm20b.c
@@ -0,0 +1,64 @@
+/*
+ * GM20B MMU
+ *
+ * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/delay.h>
+
+#include <nvgpu/timers.h>
+
+#include "bus_gm20b.h"
+#include "gk20a/gk20a.h"
+#include "gk20a/bus_gk20a.h"
+
+#include <nvgpu/hw/gm20b/hw_bus_gm20b.h>
+
+static int gm20b_bus_bar1_bind(struct gk20a *g, struct mem_desc *bar1_inst)
+{
+        struct nvgpu_timeout timeout;
+        int err = 0;
+        u64 iova = gk20a_mm_inst_block_addr(g, bar1_inst);
+        u32 ptr_v = (u32)(iova >> bar1_instance_block_shift_gk20a());
+
+        gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v);
+
+        gk20a_writel(g, bus_bar1_block_r(),
+                     gk20a_aperture_mask(g, bar1_inst,
+                       bus_bar1_block_target_sys_mem_ncoh_f(),
+                       bus_bar1_block_target_vid_mem_f()) |
+                     bus_bar1_block_mode_virtual_f() |
+                     bus_bar1_block_ptr_f(ptr_v));
+        nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER);
+        do {
+                u32 val = gk20a_readl(g, bus_bind_status_r());
+                u32 pending = bus_bind_status_bar1_pending_v(val);
+                u32 outstanding = bus_bind_status_bar1_outstanding_v(val);
+                if (!pending && !outstanding)
+                        break;
+
+                udelay(5);
+        } while (!nvgpu_timeout_expired(&timeout));
+
+        if (nvgpu_timeout_peek_expired(&timeout))
+                err = -EINVAL;
+
+        return err;
+}
+
+void gm20b_init_bus(struct gpu_ops *gops)
+{
+        gops->bus.init_hw = gk20a_bus_init_hw;
+        gops->bus.isr = gk20a_bus_isr;
+        gops->bus.read_ptimer = gk20a_read_ptimer;
+        gops->bus.bar1_bind = gm20b_bus_bar1_bind;
+}
diff --git a/drivers/gpu/nvgpu/gm20b/bus_gm20b.h b/drivers/gpu/nvgpu/gm20b/bus_gm20b.h
new file mode 100644
index 00000000..853e50a6
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm20b/bus_gm20b.h
@@ -0,0 +1,23 @@
+/*
+ * GM20B BUS
+ *
+ * Copyright (c) 2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _NVGPU_GM20B_BUS
+#define _NVGPU_GM20B_BUS
+
+struct gpu_ops;
+
+void gm20b_init_bus(struct gpu_ops *gops);
+
+#endif
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index ad041f67..684f5731 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -18,6 +18,7 @@
 #include "gk20a/gk20a.h"
 #include "gk20a/dbg_gpu_gk20a.h"
 #include "gk20a/css_gr_gk20a.h"
+#include "gk20a/bus_gk20a.h"
 
 #include "ltc_gm20b.h"
 #include "ce2_gm20b.h"
@@ -215,6 +216,7 @@ int gm20b_init_hal(struct gk20a *g)
                 }
         }
 #endif
+        gk20a_init_bus(gops);
         gm20b_init_mc(gops);
         gm20b_init_ltc(gops);
         gm20b_init_gr(gops);
@@ -238,7 +240,6 @@ int gm20b_init_hal(struct gk20a *g)
         gops->name = "gm20b";
         gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
         gops->get_litter_value = gm20b_get_litter_value;
-        gops->read_ptimer = gk20a_read_ptimer;
 
         c->twod_class = FERMI_TWOD_A;
         c->threed_class = MAXWELL_B;
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
index 18f9eec1..949a5c5d 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
@@ -13,17 +13,12 @@
  * more details.
  */
 
-#include <linux/delay.h>
-
 #include "gk20a/gk20a.h"
 
 #include "mm_gm20b.h"
 
-#include <nvgpu/timers.h>
-
 #include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
-#include <nvgpu/hw/gm20b/hw_bus_gm20b.h>
 
 static void gm20b_mm_set_big_page_size(struct gk20a *g,
                                 struct mem_desc *mem, int size)
@@ -55,34 +50,6 @@ static bool gm20b_mm_support_sparse(struct gk20a *g)
         return true;
 }
 
-static int gm20b_mm_bar1_bind(struct gk20a *g, struct mem_desc *bar1_inst)
-{
-        int retry = 1000;
-        u64 iova = gk20a_mm_inst_block_addr(g, bar1_inst);
-        u32 ptr_v = (u32)(iova >> bar1_instance_block_shift_gk20a());
-
-        gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v);
-
-        gk20a_writel(g, bus_bar1_block_r(),
-                     gk20a_aperture_mask(g, bar1_inst,
-                       bus_bar1_block_target_sys_mem_ncoh_f(),
-                       bus_bar1_block_target_vid_mem_f()) |
-                     bus_bar1_block_mode_virtual_f() |
-                     bus_bar1_block_ptr_f(ptr_v));
-        do {
-                u32 val = gk20a_readl(g, bus_bind_status_r());
-                u32 pending = bus_bind_status_bar1_pending_v(val);
-                u32 outstanding = bus_bind_status_bar1_outstanding_v(val);
-                if (!pending && !outstanding)
-                        break;
-
-                udelay(5);
-                retry--;
-        } while (retry >= 0 || !tegra_platform_is_silicon());
-
-        return retry ? -EINVAL : 0;
-}
-
 static bool gm20b_mm_is_bar1_supported(struct gk20a *g)
 {
         return true;
@@ -107,7 +74,6 @@ void gm20b_init_mm(struct gpu_ops *gops)
         gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels;
         gops->mm.init_pdb = gk20a_mm_init_pdb;
         gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw;
-        gops->mm.bar1_bind = gm20b_mm_bar1_bind;
         gops->mm.is_bar1_supported = gm20b_mm_is_bar1_supported;
         gops->mm.init_inst_block = gk20a_init_inst_block;
         gops->mm.mmu_fault_pending = gk20a_fifo_mmu_fault_pending;