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-rw-r--r--drivers/gpu/nvgpu/gm20b/fifo_gm20b.c28
-rw-r--r--drivers/gpu/nvgpu/gm20b/fifo_gm20b.h1
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c1
3 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index 8e913f23..6b462acd 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -183,3 +183,31 @@ void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f)
183 f->intr.pbdma.restartable_0 = 183 f->intr.pbdma.restartable_0 =
184 pbdma_intr_0_device_pending_f(); 184 pbdma_intr_0_device_pending_f();
185} 185}
186
187static void gm20b_fifo_set_ctx_reload(struct channel_gk20a *ch)
188{
189 struct gk20a *g = ch->g;
190 u32 channel = gk20a_readl(g, ccsr_channel_r(ch->chid));
191
192 gk20a_writel(g, ccsr_channel_r(ch->chid),
193 channel | ccsr_channel_force_ctx_reload_true_f());
194}
195
196void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch)
197{
198 struct gk20a *g = ch->g;
199 struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
200 struct channel_gk20a *temp_ch;
201
202 /* If CTX_RELOAD is set on a channel, move it to some other channel */
203 if (gk20a_fifo_channel_status_is_ctx_reload(ch->g, ch->chid)) {
204 down_read(&tsg->ch_list_lock);
205 nvgpu_list_for_each_entry(temp_ch, &tsg->ch_list, channel_gk20a, ch_entry) {
206 if (temp_ch->chid != ch->chid) {
207 gm20b_fifo_set_ctx_reload(temp_ch);
208 break;
209 }
210 }
211 up_read(&tsg->ch_list_lock);
212 }
213}
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
index 1b1b8cc1..f82ae09b 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
@@ -25,5 +25,6 @@ void gm20b_device_info_data_parse(struct gk20a *g,
25 u32 table_entry, u32 *inst_id, 25 u32 table_entry, u32 *inst_id,
26 u32 *pri_base, u32 *fault_id); 26 u32 *pri_base, u32 *fault_id);
27void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); 27void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
28void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch);
28 29
29#endif 30#endif
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 46c1e81f..9ff9fdd7 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -368,6 +368,7 @@ static const struct gpu_ops gm20b_ops = {
368 .preempt_tsg = gk20a_fifo_preempt_tsg, 368 .preempt_tsg = gk20a_fifo_preempt_tsg,
369 .enable_tsg = gk20a_enable_tsg, 369 .enable_tsg = gk20a_enable_tsg,
370 .disable_tsg = gk20a_disable_tsg, 370 .disable_tsg = gk20a_disable_tsg,
371 .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload,
371 .update_runlist = gk20a_fifo_update_runlist, 372 .update_runlist = gk20a_fifo_update_runlist,
372 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, 373 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
373 .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info, 374 .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info,