diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 387 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.h | 44 |
2 files changed, 152 insertions, 279 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 3d90938d..ceeb457a 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -16,13 +16,7 @@ | |||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #ifdef CONFIG_DEBUG_FS | ||
20 | #include <linux/debugfs.h> | ||
21 | #include <linux/uaccess.h> | ||
22 | #endif | ||
23 | |||
24 | #include "gk20a/gk20a.h" | 19 | #include "gk20a/gk20a.h" |
25 | #include "gk20a/platform_gk20a.h" | ||
26 | #include "clk_gm20b.h" | 20 | #include "clk_gm20b.h" |
27 | 21 | ||
28 | #include <nvgpu/soc.h> | 22 | #include <nvgpu/soc.h> |
@@ -48,7 +42,6 @@ | |||
48 | #define ADC_SLOPE_UV 10000 /* default ADC detection slope 10mV */ | 42 | #define ADC_SLOPE_UV 10000 /* default ADC detection slope 10mV */ |
49 | 43 | ||
50 | #define DVFS_SAFE_MARGIN 10 /* 10% */ | 44 | #define DVFS_SAFE_MARGIN 10 /* 10% */ |
51 | static unsigned long dvfs_safe_max_freq; | ||
52 | 45 | ||
53 | static struct pll_parms gpc_pll_params_b1 = { | 46 | static struct pll_parms gpc_pll_params_b1 = { |
54 | 128000, 2600000, /* freq */ | 47 | 128000, 2600000, /* freq */ |
@@ -82,9 +75,6 @@ static struct pll_parms gpc_pll_params_c1 = { | |||
82 | 75 | ||
83 | static struct pll_parms gpc_pll_params; | 76 | static struct pll_parms gpc_pll_params; |
84 | 77 | ||
85 | #ifdef CONFIG_DEBUG_FS | ||
86 | static int clk_gm20b_debugfs_init(struct gk20a *g); | ||
87 | #endif | ||
88 | static void clk_setup_slide(struct gk20a *g, u32 clk_u); | 78 | static void clk_setup_slide(struct gk20a *g, u32 clk_u); |
89 | 79 | ||
90 | #define DUMP_REG(addr_func) \ | 80 | #define DUMP_REG(addr_func) \ |
@@ -107,17 +97,6 @@ static void dump_gpc_pll(struct gk20a *g, struct pll *gpll, u32 last_cfg) | |||
107 | pr_info("\n"); | 97 | pr_info("\n"); |
108 | } | 98 | } |
109 | 99 | ||
110 | /* 1:1 match between post divider settings and divisor value */ | ||
111 | static inline u32 pl_to_div(u32 pl) | ||
112 | { | ||
113 | return pl; | ||
114 | } | ||
115 | |||
116 | static inline u32 div_to_pl(u32 div) | ||
117 | { | ||
118 | return div; | ||
119 | } | ||
120 | |||
121 | #define PLDIV_GLITCHLESS 1 | 100 | #define PLDIV_GLITCHLESS 1 |
122 | 101 | ||
123 | #if PLDIV_GLITCHLESS | 102 | #if PLDIV_GLITCHLESS |
@@ -174,19 +153,19 @@ static int clk_config_pll(struct clk_gk20a *clk, struct pll *pll, | |||
174 | max_vco_f = target_vco_f; | 153 | max_vco_f = target_vco_f; |
175 | 154 | ||
176 | /* Set PL search boundaries. */ | 155 | /* Set PL search boundaries. */ |
177 | high_PL = div_to_pl((max_vco_f + target_vco_f - 1) / target_vco_f); | 156 | high_PL = nvgpu_div_to_pl((max_vco_f + target_vco_f - 1) / target_vco_f); |
178 | high_PL = min(high_PL, pll_params->max_PL); | 157 | high_PL = min(high_PL, pll_params->max_PL); |
179 | high_PL = max(high_PL, pll_params->min_PL); | 158 | high_PL = max(high_PL, pll_params->min_PL); |
180 | 159 | ||
181 | low_PL = div_to_pl(min_vco_f / target_vco_f); | 160 | low_PL = nvgpu_div_to_pl(min_vco_f / target_vco_f); |
182 | low_PL = min(low_PL, pll_params->max_PL); | 161 | low_PL = min(low_PL, pll_params->max_PL); |
183 | low_PL = max(low_PL, pll_params->min_PL); | 162 | low_PL = max(low_PL, pll_params->min_PL); |
184 | 163 | ||
185 | gk20a_dbg_info("low_PL %d(div%d), high_PL %d(div%d)", | 164 | gk20a_dbg_info("low_PL %d(div%d), high_PL %d(div%d)", |
186 | low_PL, pl_to_div(low_PL), high_PL, pl_to_div(high_PL)); | 165 | low_PL, nvgpu_pl_to_div(low_PL), high_PL, nvgpu_pl_to_div(high_PL)); |
187 | 166 | ||
188 | for (pl = low_PL; pl <= high_PL; pl++) { | 167 | for (pl = low_PL; pl <= high_PL; pl++) { |
189 | target_vco_f = target_clk_f * pl_to_div(pl); | 168 | target_vco_f = target_clk_f * nvgpu_pl_to_div(pl); |
190 | 169 | ||
191 | for (m = pll_params->min_M; m <= pll_params->max_M; m++) { | 170 | for (m = pll_params->min_M; m <= pll_params->max_M; m++) { |
192 | u_f = ref_clk_f / m; | 171 | u_f = ref_clk_f / m; |
@@ -211,8 +190,8 @@ static int clk_config_pll(struct clk_gk20a *clk, struct pll *pll, | |||
211 | vco_f = ref_clk_f * n / m; | 190 | vco_f = ref_clk_f * n / m; |
212 | 191 | ||
213 | if (vco_f >= min_vco_f && vco_f <= max_vco_f) { | 192 | if (vco_f >= min_vco_f && vco_f <= max_vco_f) { |
214 | lwv = (vco_f + (pl_to_div(pl) / 2)) | 193 | lwv = (vco_f + (nvgpu_pl_to_div(pl) / 2)) |
215 | / pl_to_div(pl); | 194 | / nvgpu_pl_to_div(pl); |
216 | delta = abs(lwv - target_clk_f); | 195 | delta = abs(lwv - target_clk_f); |
217 | 196 | ||
218 | if (delta < best_delta) { | 197 | if (delta < best_delta) { |
@@ -247,12 +226,12 @@ found_match: | |||
247 | pll->PL = best_PL; | 226 | pll->PL = best_PL; |
248 | 227 | ||
249 | /* save current frequency */ | 228 | /* save current frequency */ |
250 | pll->freq = ref_clk_f * pll->N / (pll->M * pl_to_div(pll->PL)); | 229 | pll->freq = ref_clk_f * pll->N / (pll->M * nvgpu_pl_to_div(pll->PL)); |
251 | 230 | ||
252 | *target_freq = pll->freq; | 231 | *target_freq = pll->freq; |
253 | 232 | ||
254 | gk20a_dbg_clk("actual target freq %d kHz, M %d, N %d, PL %d(div%d)", | 233 | gk20a_dbg_clk("actual target freq %d kHz, M %d, N %d, PL %d(div%d)", |
255 | *target_freq, pll->M, pll->N, pll->PL, pl_to_div(pll->PL)); | 234 | *target_freq, pll->M, pll->N, pll->PL, nvgpu_pl_to_div(pll->PL)); |
256 | 235 | ||
257 | gk20a_dbg_fn("done"); | 236 | gk20a_dbg_fn("done"); |
258 | 237 | ||
@@ -965,7 +944,7 @@ static void clk_config_pll_safe_dvfs(struct gk20a *g, struct pll *gpll) | |||
965 | { | 944 | { |
966 | u32 nsafe, nmin; | 945 | u32 nsafe, nmin; |
967 | 946 | ||
968 | if (gpll->freq > dvfs_safe_max_freq) | 947 | if (gpll->freq > g->clk.dvfs_safe_max_freq) |
969 | gpll->freq = gpll->freq * (100 - DVFS_SAFE_MARGIN) / 100; | 948 | gpll->freq = gpll->freq * (100 - DVFS_SAFE_MARGIN) / 100; |
970 | 949 | ||
971 | nmin = DIV_ROUND_UP(gpll->M * gpc_pll_params.min_vco, gpll->clk_in); | 950 | nmin = DIV_ROUND_UP(gpll->M * gpc_pll_params.min_vco, gpll->clk_in); |
@@ -994,7 +973,7 @@ static void clk_config_pll_safe_dvfs(struct gk20a *g, struct pll *gpll) | |||
994 | clk_config_dvfs_ndiv(gpll->dvfs.mv, gpll->N, &gpll->dvfs); | 973 | clk_config_dvfs_ndiv(gpll->dvfs.mv, gpll->N, &gpll->dvfs); |
995 | 974 | ||
996 | gk20a_dbg_clk("safe freq %d kHz, M %d, N %d, PL %d(div%d), mV(cal) %d(%d), DC %d", | 975 | gk20a_dbg_clk("safe freq %d kHz, M %d, N %d, PL %d(div%d), mV(cal) %d(%d), DC %d", |
997 | gpll->freq, gpll->M, gpll->N, gpll->PL, pl_to_div(gpll->PL), | 976 | gpll->freq, gpll->M, gpll->N, gpll->PL, nvgpu_pl_to_div(gpll->PL), |
998 | gpll->dvfs.mv, gpll->dvfs.uv_cal / 1000, gpll->dvfs.dfs_coeff); | 977 | gpll->dvfs.mv, gpll->dvfs.uv_cal / 1000, gpll->dvfs.dfs_coeff); |
999 | } | 978 | } |
1000 | 979 | ||
@@ -1038,7 +1017,7 @@ static int clk_program_na_gpc_pll(struct gk20a *g, struct pll *gpll_new, | |||
1038 | * i.e., it is low enough to be safe at any voltage in operating range | 1017 | * i.e., it is low enough to be safe at any voltage in operating range |
1039 | * with zero DVFS coefficient. | 1018 | * with zero DVFS coefficient. |
1040 | */ | 1019 | */ |
1041 | if (gpll_old->freq > dvfs_safe_max_freq) { | 1020 | if (gpll_old->freq > g->clk.dvfs_safe_max_freq) { |
1042 | if (gpll_old->dvfs.mv < gpll_new->dvfs.mv) { | 1021 | if (gpll_old->dvfs.mv < gpll_new->dvfs.mv) { |
1043 | gpll_safe = *gpll_old; | 1022 | gpll_safe = *gpll_old; |
1044 | gpll_safe.dvfs.mv = gpll_new->dvfs.mv; | 1023 | gpll_safe.dvfs.mv = gpll_new->dvfs.mv; |
@@ -1070,7 +1049,7 @@ static int clk_program_na_gpc_pll(struct gk20a *g, struct pll *gpll_new, | |||
1070 | 1049 | ||
1071 | gk20a_dbg_clk("config_pll %d kHz, M %d, N %d, PL %d(div%d), mV(cal) %d(%d), DC %d", | 1050 | gk20a_dbg_clk("config_pll %d kHz, M %d, N %d, PL %d(div%d), mV(cal) %d(%d), DC %d", |
1072 | gpll_new->freq, gpll_new->M, gpll_new->N, gpll_new->PL, | 1051 | gpll_new->freq, gpll_new->M, gpll_new->N, gpll_new->PL, |
1073 | pl_to_div(gpll_new->PL), | 1052 | nvgpu_pl_to_div(gpll_new->PL), |
1074 | max(gpll_new->dvfs.mv, gpll_old->dvfs.mv), | 1053 | max(gpll_new->dvfs.mv, gpll_old->dvfs.mv), |
1075 | gpll_new->dvfs.uv_cal / 1000, gpll_new->dvfs.dfs_coeff); | 1054 | gpll_new->dvfs.uv_cal / 1000, gpll_new->dvfs.dfs_coeff); |
1076 | 1055 | ||
@@ -1120,6 +1099,11 @@ static int clk_disable_gpcpll(struct gk20a *g, int allow_slide) | |||
1120 | return 0; | 1099 | return 0; |
1121 | } | 1100 | } |
1122 | 1101 | ||
1102 | struct pll_parms *gm20b_get_gpc_pll_parms(void) | ||
1103 | { | ||
1104 | return &gpc_pll_params; | ||
1105 | } | ||
1106 | |||
1123 | int gm20b_init_clk_setup_sw(struct gk20a *g) | 1107 | int gm20b_init_clk_setup_sw(struct gk20a *g) |
1124 | { | 1108 | { |
1125 | struct clk_gk20a *clk = &g->clk; | 1109 | struct clk_gk20a *clk = &g->clk; |
@@ -1156,9 +1140,9 @@ int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1156 | 1140 | ||
1157 | safe_rate = g->ops.clk.get_fmax_at_vmin_safe(clk); | 1141 | safe_rate = g->ops.clk.get_fmax_at_vmin_safe(clk); |
1158 | safe_rate = safe_rate * (100 - DVFS_SAFE_MARGIN) / 100; | 1142 | safe_rate = safe_rate * (100 - DVFS_SAFE_MARGIN) / 100; |
1159 | dvfs_safe_max_freq = rate_gpu_to_gpc2clk(safe_rate); | 1143 | clk->dvfs_safe_max_freq = rate_gpu_to_gpc2clk(safe_rate); |
1160 | clk->gpc_pll.PL = (dvfs_safe_max_freq == 0) ? 0 : | 1144 | clk->gpc_pll.PL = (clk->dvfs_safe_max_freq == 0) ? 0 : |
1161 | DIV_ROUND_UP(gpc_pll_params.min_vco, dvfs_safe_max_freq); | 1145 | DIV_ROUND_UP(gpc_pll_params.min_vco, clk->dvfs_safe_max_freq); |
1162 | 1146 | ||
1163 | /* Initial freq: low enough to be safe at Vmin (default 1/3 VCO min) */ | 1147 | /* Initial freq: low enough to be safe at Vmin (default 1/3 VCO min) */ |
1164 | clk->gpc_pll.M = 1; | 1148 | clk->gpc_pll.M = 1; |
@@ -1166,7 +1150,7 @@ int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1166 | clk->gpc_pll.clk_in); | 1150 | clk->gpc_pll.clk_in); |
1167 | clk->gpc_pll.PL = max(clk->gpc_pll.PL, 3U); | 1151 | clk->gpc_pll.PL = max(clk->gpc_pll.PL, 3U); |
1168 | clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N; | 1152 | clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N; |
1169 | clk->gpc_pll.freq /= pl_to_div(clk->gpc_pll.PL); | 1153 | clk->gpc_pll.freq /= nvgpu_pl_to_div(clk->gpc_pll.PL); |
1170 | 1154 | ||
1171 | /* | 1155 | /* |
1172 | * All production parts should have ADC fuses burnt. Therefore, check | 1156 | * All production parts should have ADC fuses burnt. Therefore, check |
@@ -1408,12 +1392,13 @@ static int gm20b_init_clk_support(struct gk20a *g) | |||
1408 | if (err) | 1392 | if (err) |
1409 | return err; | 1393 | return err; |
1410 | 1394 | ||
1411 | #ifdef CONFIG_DEBUG_FS | 1395 | if (!clk->debugfs_set && g->ops.clk.init_debugfs) { |
1412 | if (!clk->debugfs_set) { | 1396 | err = g->ops.clk.init_debugfs(g); |
1413 | if (!clk_gm20b_debugfs_init(g)) | 1397 | if (err) |
1414 | clk->debugfs_set = true; | 1398 | return err; |
1399 | clk->debugfs_set = true; | ||
1415 | } | 1400 | } |
1416 | #endif | 1401 | |
1417 | return err; | 1402 | return err; |
1418 | } | 1403 | } |
1419 | 1404 | ||
@@ -1435,168 +1420,36 @@ static int gm20b_suspend_clk_support(struct gk20a *g) | |||
1435 | return ret; | 1420 | return ret; |
1436 | } | 1421 | } |
1437 | 1422 | ||
1438 | void gm20b_init_clk_ops(struct gpu_ops *gops) | 1423 | static int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val) |
1439 | { | 1424 | { |
1440 | gops->clk.init_clk_support = gm20b_init_clk_support; | 1425 | struct gk20a *g = clk->g; |
1441 | gops->clk.suspend_clk_support = gm20b_suspend_clk_support; | 1426 | struct pll_parms *gpc_pll_params = gm20b_get_gpc_pll_parms(); |
1442 | } | 1427 | u32 det_out; |
1443 | 1428 | int err; | |
1444 | #ifdef CONFIG_DEBUG_FS | ||
1445 | |||
1446 | static int rate_get(void *data, u64 *val) | ||
1447 | { | ||
1448 | struct gk20a *g = (struct gk20a *)data; | ||
1449 | struct clk_gk20a *clk = &g->clk; | ||
1450 | 1429 | ||
1451 | *val = (u64)rate_gpc2clk_to_gpu(clk->gpc_pll.freq); | 1430 | if (clk->gpc_pll.mode != GPC_PLL_MODE_DVFS) |
1452 | return 0; | 1431 | return -ENOSYS; |
1453 | } | ||
1454 | static int rate_set(void *data, u64 val) | ||
1455 | { | ||
1456 | struct gk20a *g = (struct gk20a *)data; | ||
1457 | return g->ops.clk.set_rate(g, CTRL_CLK_DOMAIN_GPCCLK, (u32)val); | ||
1458 | } | ||
1459 | DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n"); | ||
1460 | 1432 | ||
1461 | static int pll_reg_show(struct seq_file *s, void *data) | 1433 | err = gk20a_busy(g); |
1462 | { | 1434 | if (err) |
1463 | struct gk20a *g = s->private; | 1435 | return err; |
1464 | u32 reg, m, n, pl, f, d, dmax, doffs; | ||
1465 | 1436 | ||
1466 | nvgpu_mutex_acquire(&g->clk.clk_mutex); | 1437 | nvgpu_mutex_acquire(&g->clk.clk_mutex); |
1467 | if (!g->clk.clk_hw_on) { | ||
1468 | seq_printf(s, "%s powered down - no access to registers\n", | ||
1469 | g->name); | ||
1470 | nvgpu_mutex_release(&g->clk.clk_mutex); | ||
1471 | return 0; | ||
1472 | } | ||
1473 | |||
1474 | reg = gk20a_readl(g, trim_sys_bypassctrl_r()); | ||
1475 | seq_printf(s, "bypassctrl = %s, ", reg ? "bypass" : "vco"); | ||
1476 | reg = gk20a_readl(g, trim_sys_sel_vco_r()); | ||
1477 | seq_printf(s, "sel_vco = %s, ", reg ? "vco" : "bypass"); | ||
1478 | 1438 | ||
1479 | reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 1439 | det_out = gk20a_readl(g, trim_sys_gpcpll_cfg3_r()); |
1480 | seq_printf(s, "cfg = 0x%x : %s : %s : %s\n", reg, | 1440 | det_out = trim_sys_gpcpll_cfg3_dfs_testout_v(det_out); |
1481 | trim_sys_gpcpll_cfg_enable_v(reg) ? "enabled" : "disabled", | 1441 | *val = div64_u64((u64)det_out * gpc_pll_params->uvdet_slope + |
1482 | trim_sys_gpcpll_cfg_pll_lock_v(reg) ? "locked" : "unlocked", | 1442 | gpc_pll_params->uvdet_offs, 1000ULL); |
1483 | trim_sys_gpcpll_cfg_sync_mode_v(reg) ? "sync_on" : "sync_off"); | ||
1484 | 1443 | ||
1485 | reg = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); | ||
1486 | m = trim_sys_gpcpll_coeff_mdiv_v(reg); | ||
1487 | n = trim_sys_gpcpll_coeff_ndiv_v(reg); | ||
1488 | pl = trim_sys_gpcpll_coeff_pldiv_v(reg); | ||
1489 | f = g->clk.gpc_pll.clk_in * n / (m * pl_to_div(pl)); | ||
1490 | seq_printf(s, "coef = 0x%x : m = %u : n = %u : pl = %u", reg, m, n, pl); | ||
1491 | seq_printf(s, " : pll_f(gpu_f) = %u(%u) kHz\n", f, f/2); | ||
1492 | reg = gk20a_readl(g, trim_sys_gpcpll_dvfs0_r()); | ||
1493 | d = trim_sys_gpcpll_dvfs0_dfs_coeff_v(reg); | ||
1494 | dmax = trim_sys_gpcpll_dvfs0_dfs_det_max_v(reg); | ||
1495 | doffs = trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(reg); | ||
1496 | seq_printf(s, "dvfs0 = 0x%x : d = %u : dmax = %u : doffs = %u\n", | ||
1497 | reg, d, dmax, doffs); | ||
1498 | nvgpu_mutex_release(&g->clk.clk_mutex); | 1444 | nvgpu_mutex_release(&g->clk.clk_mutex); |
1499 | return 0; | ||
1500 | } | ||
1501 | |||
1502 | static int pll_reg_open(struct inode *inode, struct file *file) | ||
1503 | { | ||
1504 | return single_open(file, pll_reg_show, inode->i_private); | ||
1505 | } | ||
1506 | |||
1507 | static const struct file_operations pll_reg_fops = { | ||
1508 | .open = pll_reg_open, | ||
1509 | .read = seq_read, | ||
1510 | .llseek = seq_lseek, | ||
1511 | .release = single_release, | ||
1512 | }; | ||
1513 | |||
1514 | static int pll_reg_raw_show(struct seq_file *s, void *data) | ||
1515 | { | ||
1516 | struct gk20a *g = s->private; | ||
1517 | u32 reg; | ||
1518 | 1445 | ||
1519 | nvgpu_mutex_acquire(&g->clk.clk_mutex); | 1446 | gk20a_idle(g); |
1520 | if (!g->clk.clk_hw_on) { | ||
1521 | seq_printf(s, "%s powered down - no access to registers\n", | ||
1522 | g->name); | ||
1523 | nvgpu_mutex_release(&g->clk.clk_mutex); | ||
1524 | return 0; | ||
1525 | } | ||
1526 | |||
1527 | seq_puts(s, "GPCPLL REGISTERS:\n"); | ||
1528 | for (reg = trim_sys_gpcpll_cfg_r(); reg <= trim_sys_gpcpll_dvfs2_r(); | ||
1529 | reg += sizeof(u32)) | ||
1530 | seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg)); | ||
1531 | |||
1532 | seq_puts(s, "\nGPC CLK OUT REGISTERS:\n"); | ||
1533 | |||
1534 | reg = trim_sys_sel_vco_r(); | ||
1535 | seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg)); | ||
1536 | reg = trim_sys_gpc2clk_out_r(); | ||
1537 | seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg)); | ||
1538 | reg = trim_sys_bypassctrl_r(); | ||
1539 | seq_printf(s, "[0x%02x] = 0x%08x\n", reg, gk20a_readl(g, reg)); | ||
1540 | |||
1541 | nvgpu_mutex_release(&g->clk.clk_mutex); | ||
1542 | return 0; | 1447 | return 0; |
1543 | } | 1448 | } |
1544 | 1449 | ||
1545 | static int pll_reg_raw_open(struct inode *inode, struct file *file) | 1450 | static int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val) |
1546 | { | 1451 | { |
1547 | return single_open(file, pll_reg_raw_show, inode->i_private); | 1452 | struct gk20a *g = clk->g; |
1548 | } | ||
1549 | |||
1550 | static ssize_t pll_reg_raw_write(struct file *file, | ||
1551 | const char __user *userbuf, size_t count, loff_t *ppos) | ||
1552 | { | ||
1553 | struct gk20a *g = file->f_path.dentry->d_inode->i_private; | ||
1554 | char buf[80]; | ||
1555 | u32 reg, val; | ||
1556 | |||
1557 | if (sizeof(buf) <= count) | ||
1558 | return -EINVAL; | ||
1559 | |||
1560 | if (copy_from_user(buf, userbuf, count)) | ||
1561 | return -EFAULT; | ||
1562 | |||
1563 | /* terminate buffer and trim - white spaces may be appended | ||
1564 | * at the end when invoked from shell command line */ | ||
1565 | buf[count] = '\0'; | ||
1566 | strim(buf); | ||
1567 | |||
1568 | if (sscanf(buf, "[0x%x] = 0x%x", ®, &val) != 2) | ||
1569 | return -EINVAL; | ||
1570 | |||
1571 | if (((reg < trim_sys_gpcpll_cfg_r()) || | ||
1572 | (reg > trim_sys_gpcpll_dvfs2_r())) && | ||
1573 | (reg != trim_sys_sel_vco_r()) && | ||
1574 | (reg != trim_sys_gpc2clk_out_r()) && | ||
1575 | (reg != trim_sys_bypassctrl_r())) | ||
1576 | return -EPERM; | ||
1577 | |||
1578 | nvgpu_mutex_acquire(&g->clk.clk_mutex); | ||
1579 | if (!g->clk.clk_hw_on) { | ||
1580 | nvgpu_mutex_release(&g->clk.clk_mutex); | ||
1581 | return -EBUSY; | ||
1582 | } | ||
1583 | gk20a_writel(g, reg, val); | ||
1584 | nvgpu_mutex_release(&g->clk.clk_mutex); | ||
1585 | return count; | ||
1586 | } | ||
1587 | |||
1588 | static const struct file_operations pll_reg_raw_fops = { | ||
1589 | .open = pll_reg_raw_open, | ||
1590 | .read = seq_read, | ||
1591 | .write = pll_reg_raw_write, | ||
1592 | .llseek = seq_lseek, | ||
1593 | .release = single_release, | ||
1594 | }; | ||
1595 | |||
1596 | static int monitor_get(void *data, u64 *val) | ||
1597 | { | ||
1598 | struct gk20a *g = (struct gk20a *)data; | ||
1599 | struct clk_gk20a *clk = &g->clk; | ||
1600 | u32 clk_slowdown, clk_slowdown_save; | 1453 | u32 clk_slowdown, clk_slowdown_save; |
1601 | int err; | 1454 | int err; |
1602 | 1455 | ||
@@ -1627,7 +1480,8 @@ static int monitor_get(void *data, u64 *val) | |||
1627 | /* start */ | 1480 | /* start */ |
1628 | 1481 | ||
1629 | /* It should take less than 25us to finish 800 cycle of 38.4MHz. | 1482 | /* It should take less than 25us to finish 800 cycle of 38.4MHz. |
1630 | But longer than 100us delay is required here. */ | 1483 | * But longer than 100us delay is required here. |
1484 | */ | ||
1631 | gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0)); | 1485 | gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0)); |
1632 | nvgpu_udelay(200); | 1486 | nvgpu_udelay(200); |
1633 | 1487 | ||
@@ -1646,109 +1500,84 @@ static int monitor_get(void *data, u64 *val) | |||
1646 | 1500 | ||
1647 | if (count1 != count2) | 1501 | if (count1 != count2) |
1648 | return -EBUSY; | 1502 | return -EBUSY; |
1503 | |||
1649 | return 0; | 1504 | return 0; |
1650 | } | 1505 | } |
1651 | DEFINE_SIMPLE_ATTRIBUTE(monitor_fops, monitor_get, NULL, "%llu\n"); | ||
1652 | 1506 | ||
1653 | static int voltage_get(void *data, u64 *val) | 1507 | int gm20b_clk_pll_reg_write(struct gk20a *g, u32 reg, u32 val) |
1654 | { | 1508 | { |
1655 | struct gk20a *g = (struct gk20a *)data; | 1509 | if (((reg < trim_sys_gpcpll_cfg_r()) || |
1656 | struct clk_gk20a *clk = &g->clk; | 1510 | (reg > trim_sys_gpcpll_dvfs2_r())) && |
1657 | u32 det_out; | 1511 | (reg != trim_sys_sel_vco_r()) && |
1658 | int err; | 1512 | (reg != trim_sys_gpc2clk_out_r()) && |
1659 | 1513 | (reg != trim_sys_bypassctrl_r())) | |
1660 | if (clk->gpc_pll.mode != GPC_PLL_MODE_DVFS) | 1514 | return -EPERM; |
1661 | return -ENOSYS; | ||
1662 | |||
1663 | err = gk20a_busy(g); | ||
1664 | if (err) | ||
1665 | return err; | ||
1666 | 1515 | ||
1667 | nvgpu_mutex_acquire(&g->clk.clk_mutex); | 1516 | nvgpu_mutex_acquire(&g->clk.clk_mutex); |
1668 | 1517 | if (!g->clk.clk_hw_on) { | |
1669 | det_out = gk20a_readl(g, trim_sys_gpcpll_cfg3_r()); | 1518 | nvgpu_mutex_release(&g->clk.clk_mutex); |
1670 | det_out = trim_sys_gpcpll_cfg3_dfs_testout_v(det_out); | 1519 | return -EINVAL; |
1671 | *val = div64_u64((u64)det_out * gpc_pll_params.uvdet_slope + | 1520 | } |
1672 | gpc_pll_params.uvdet_offs, 1000ULL); | 1521 | gk20a_writel(g, reg, val); |
1673 | |||
1674 | nvgpu_mutex_release(&g->clk.clk_mutex); | 1522 | nvgpu_mutex_release(&g->clk.clk_mutex); |
1675 | 1523 | ||
1676 | gk20a_idle(g); | ||
1677 | return 0; | 1524 | return 0; |
1678 | } | 1525 | } |
1679 | DEFINE_SIMPLE_ATTRIBUTE(voltage_fops, voltage_get, NULL, "%llu\n"); | ||
1680 | 1526 | ||
1681 | static int pll_param_show(struct seq_file *s, void *data) | 1527 | int gm20b_clk_get_pll_debug_data(struct gk20a *g, |
1528 | struct nvgpu_clk_pll_debug_data *d) | ||
1682 | { | 1529 | { |
1683 | seq_printf(s, "ADC offs = %d uV, ADC slope = %d uV, VCO ctrl = 0x%x\n", | 1530 | u32 reg; |
1684 | gpc_pll_params.uvdet_offs, gpc_pll_params.uvdet_slope, | ||
1685 | gpc_pll_params.vco_ctrl); | ||
1686 | return 0; | ||
1687 | } | ||
1688 | 1531 | ||
1689 | static int pll_param_open(struct inode *inode, struct file *file) | 1532 | nvgpu_mutex_acquire(&g->clk.clk_mutex); |
1690 | { | 1533 | if (!g->clk.clk_hw_on) { |
1691 | return single_open(file, pll_param_show, inode->i_private); | 1534 | nvgpu_mutex_release(&g->clk.clk_mutex); |
1692 | } | 1535 | return -EINVAL; |
1536 | } | ||
1693 | 1537 | ||
1694 | static const struct file_operations pll_param_fops = { | 1538 | d->trim_sys_bypassctrl_reg = trim_sys_bypassctrl_r(); |
1695 | .open = pll_param_open, | 1539 | d->trim_sys_bypassctrl_val = gk20a_readl(g, trim_sys_bypassctrl_r()); |
1696 | .read = seq_read, | 1540 | d->trim_sys_sel_vco_reg = trim_sys_sel_vco_r(); |
1697 | .llseek = seq_lseek, | 1541 | d->trim_sys_sel_vco_val = gk20a_readl(g, trim_sys_sel_vco_r()); |
1698 | .release = single_release, | 1542 | d->trim_sys_gpc2clk_out_reg = trim_sys_gpc2clk_out_r(); |
1699 | }; | 1543 | d->trim_sys_gpc2clk_out_val = gk20a_readl(g, trim_sys_gpc2clk_out_r()); |
1544 | d->trim_sys_gpcpll_cfg_reg = trim_sys_gpcpll_cfg_r(); | ||
1545 | d->trim_sys_gpcpll_dvfs2_reg = trim_sys_gpcpll_dvfs2_r(); | ||
1700 | 1546 | ||
1701 | static int clk_gm20b_debugfs_init(struct gk20a *g) | 1547 | reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
1702 | { | 1548 | d->trim_sys_gpcpll_cfg_val = reg; |
1703 | struct dentry *d; | 1549 | d->trim_sys_gpcpll_cfg_enabled = trim_sys_gpcpll_cfg_enable_v(reg); |
1704 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | 1550 | d->trim_sys_gpcpll_cfg_locked = trim_sys_gpcpll_cfg_pll_lock_v(reg); |
1705 | 1551 | d->trim_sys_gpcpll_cfg_sync_on = trim_sys_gpcpll_cfg_sync_mode_v(reg); | |
1706 | d = debugfs_create_file( | ||
1707 | "rate", S_IRUGO|S_IWUSR, platform->debugfs, g, &rate_fops); | ||
1708 | if (!d) | ||
1709 | goto err_out; | ||
1710 | |||
1711 | d = debugfs_create_file( | ||
1712 | "pll_reg", S_IRUGO, platform->debugfs, g, &pll_reg_fops); | ||
1713 | if (!d) | ||
1714 | goto err_out; | ||
1715 | |||
1716 | d = debugfs_create_file("pll_reg_raw", | ||
1717 | S_IRUGO, platform->debugfs, g, &pll_reg_raw_fops); | ||
1718 | if (!d) | ||
1719 | goto err_out; | ||
1720 | |||
1721 | d = debugfs_create_file( | ||
1722 | "monitor", S_IRUGO, platform->debugfs, g, &monitor_fops); | ||
1723 | if (!d) | ||
1724 | goto err_out; | ||
1725 | |||
1726 | d = debugfs_create_file( | ||
1727 | "voltage", S_IRUGO, platform->debugfs, g, &voltage_fops); | ||
1728 | if (!d) | ||
1729 | goto err_out; | ||
1730 | |||
1731 | d = debugfs_create_file( | ||
1732 | "pll_param", S_IRUGO, platform->debugfs, g, &pll_param_fops); | ||
1733 | if (!d) | ||
1734 | goto err_out; | ||
1735 | |||
1736 | d = debugfs_create_u32("pll_na_mode", S_IRUGO, platform->debugfs, | ||
1737 | (u32 *)&g->clk.gpc_pll.mode); | ||
1738 | if (!d) | ||
1739 | goto err_out; | ||
1740 | |||
1741 | d = debugfs_create_u32("fmax2x_at_vmin_safe_t", S_IRUGO, | ||
1742 | platform->debugfs, (u32 *)&dvfs_safe_max_freq); | ||
1743 | if (!d) | ||
1744 | goto err_out; | ||
1745 | 1552 | ||
1746 | return 0; | 1553 | reg = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); |
1554 | d->trim_sys_gpcpll_coeff_val = reg; | ||
1555 | d->trim_sys_gpcpll_coeff_mdiv = trim_sys_gpcpll_coeff_mdiv_v(reg); | ||
1556 | d->trim_sys_gpcpll_coeff_ndiv = trim_sys_gpcpll_coeff_ndiv_v(reg); | ||
1557 | d->trim_sys_gpcpll_coeff_pldiv = trim_sys_gpcpll_coeff_pldiv_v(reg); | ||
1558 | |||
1559 | reg = gk20a_readl(g, trim_sys_gpcpll_dvfs0_r()); | ||
1560 | d->trim_sys_gpcpll_dvfs0_val = reg; | ||
1561 | d->trim_sys_gpcpll_dvfs0_dfs_coeff = | ||
1562 | trim_sys_gpcpll_dvfs0_dfs_coeff_v(reg); | ||
1563 | d->trim_sys_gpcpll_dvfs0_dfs_det_max = | ||
1564 | trim_sys_gpcpll_dvfs0_dfs_det_max_v(reg); | ||
1565 | d->trim_sys_gpcpll_dvfs0_dfs_dc_offset = | ||
1566 | trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(reg); | ||
1747 | 1567 | ||
1748 | err_out: | 1568 | nvgpu_mutex_release(&g->clk.clk_mutex); |
1749 | pr_err("%s: Failed to make debugfs node\n", __func__); | 1569 | return 0; |
1750 | debugfs_remove_recursive(platform->debugfs); | ||
1751 | return -ENOMEM; | ||
1752 | } | 1570 | } |
1753 | 1571 | ||
1754 | #endif /* CONFIG_DEBUG_FS */ | 1572 | void gm20b_init_clk_ops(struct gpu_ops *gops) |
1573 | { | ||
1574 | gops->clk.init_clk_support = gm20b_init_clk_support; | ||
1575 | gops->clk.suspend_clk_support = gm20b_suspend_clk_support; | ||
1576 | #ifdef CONFIG_DEBUG_FS | ||
1577 | gops->clk.init_debugfs = gm20b_clk_init_debugfs; | ||
1578 | #endif | ||
1579 | gops->clk.get_voltage = gm20b_clk_get_voltage; | ||
1580 | gops->clk.get_gpcclk_clock_counter = gm20b_clk_get_gpcclk_clock_counter; | ||
1581 | gops->clk.pll_reg_write = gm20b_clk_pll_reg_write; | ||
1582 | gops->clk.get_pll_debug_data = gm20b_clk_get_pll_debug_data; | ||
1583 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h index f7912345..1e06d651 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h | |||
@@ -21,6 +21,35 @@ | |||
21 | 21 | ||
22 | #include <nvgpu/lock.h> | 22 | #include <nvgpu/lock.h> |
23 | 23 | ||
24 | struct nvgpu_clk_pll_debug_data { | ||
25 | u32 trim_sys_sel_vco_reg; | ||
26 | u32 trim_sys_sel_vco_val; | ||
27 | |||
28 | u32 trim_sys_gpc2clk_out_reg; | ||
29 | u32 trim_sys_gpc2clk_out_val; | ||
30 | |||
31 | u32 trim_sys_bypassctrl_reg; | ||
32 | u32 trim_sys_bypassctrl_val; | ||
33 | |||
34 | u32 trim_sys_gpcpll_cfg_reg; | ||
35 | u32 trim_sys_gpcpll_dvfs2_reg; | ||
36 | |||
37 | u32 trim_sys_gpcpll_cfg_val; | ||
38 | bool trim_sys_gpcpll_cfg_enabled; | ||
39 | bool trim_sys_gpcpll_cfg_locked; | ||
40 | bool trim_sys_gpcpll_cfg_sync_on; | ||
41 | |||
42 | u32 trim_sys_gpcpll_coeff_val; | ||
43 | u32 trim_sys_gpcpll_coeff_mdiv; | ||
44 | u32 trim_sys_gpcpll_coeff_ndiv; | ||
45 | u32 trim_sys_gpcpll_coeff_pldiv; | ||
46 | |||
47 | u32 trim_sys_gpcpll_dvfs0_val; | ||
48 | u32 trim_sys_gpcpll_dvfs0_dfs_coeff; | ||
49 | u32 trim_sys_gpcpll_dvfs0_dfs_det_max; | ||
50 | u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset; | ||
51 | }; | ||
52 | |||
24 | void gm20b_init_clk_ops(struct gpu_ops *gops); | 53 | void gm20b_init_clk_ops(struct gpu_ops *gops); |
25 | 54 | ||
26 | int gm20b_init_clk_setup_sw(struct gk20a *g); | 55 | int gm20b_init_clk_setup_sw(struct gk20a *g); |
@@ -33,5 +62,20 @@ int gm20b_gpcclk_set_rate(struct clk_gk20a *clk, unsigned long rate, | |||
33 | unsigned long parent_rate); | 62 | unsigned long parent_rate); |
34 | long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate, | 63 | long gm20b_round_rate(struct clk_gk20a *clk, unsigned long rate, |
35 | unsigned long *parent_rate); | 64 | unsigned long *parent_rate); |
65 | struct pll_parms *gm20b_get_gpc_pll_parms(void); | ||
66 | #ifdef CONFIG_DEBUG_FS | ||
67 | int gm20b_clk_init_debugfs(struct gk20a *g); | ||
68 | #endif | ||
69 | |||
70 | /* 1:1 match between post divider settings and divisor value */ | ||
71 | static inline u32 nvgpu_pl_to_div(u32 pl) | ||
72 | { | ||
73 | return pl; | ||
74 | } | ||
75 | |||
76 | static inline u32 nvgpu_div_to_pl(u32 div) | ||
77 | { | ||
78 | return div; | ||
79 | } | ||
36 | 80 | ||
37 | #endif /* _NVHOST_CLK_GM20B_H_ */ | 81 | #endif /* _NVHOST_CLK_GM20B_H_ */ |