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path: root/drivers/gpu/nvgpu/gm20b
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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r--drivers/gpu/nvgpu/gm20b/clk_gm20b.c18
1 files changed, 14 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index e28a31c8..addc27bb 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -71,6 +71,7 @@ static struct pll_parms gpc_pll_params_c1 = {
71 500, /* Locking and ramping timeout */ 71 500, /* Locking and ramping timeout */
72 40, /* Lock delay in NA mode */ 72 40, /* Lock delay in NA mode */
73 5, /* IDDQ mode exit delay */ 73 5, /* IDDQ mode exit delay */
74 0x3 << 10, /* DFS control settings */
74}; 75};
75 76
76static struct pll_parms gpc_pll_params; 77static struct pll_parms gpc_pll_params;
@@ -411,7 +412,7 @@ static void __maybe_unused clk_set_dfs_det_max(struct gk20a *g, u32 dfs_det_max)
411 412
412static void clk_set_dfs_ext_cal(struct gk20a *g, u32 dfs_det_cal) 413static void clk_set_dfs_ext_cal(struct gk20a *g, u32 dfs_det_cal)
413{ 414{
414 u32 data; 415 u32 data, ctrl;
415 416
416 data = gk20a_readl(g, trim_gpc_bcast_gpcpll_dvfs2_r()); 417 data = gk20a_readl(g, trim_gpc_bcast_gpcpll_dvfs2_r());
417 data &= ~(BIT(DFS_DET_RANGE + 1) - 1); 418 data &= ~(BIT(DFS_DET_RANGE + 1) - 1);
@@ -420,10 +421,11 @@ static void clk_set_dfs_ext_cal(struct gk20a *g, u32 dfs_det_cal)
420 421
421 data = gk20a_readl(g, trim_sys_gpcpll_dvfs1_r()); 422 data = gk20a_readl(g, trim_sys_gpcpll_dvfs1_r());
422 nvgpu_udelay(1); 423 nvgpu_udelay(1);
423 if (~trim_sys_gpcpll_dvfs1_dfs_ctrl_v(data) & DFS_EXT_CAL_EN) { 424 ctrl = trim_sys_gpcpll_dvfs1_dfs_ctrl_v(data);
425 if (~ctrl & DFS_EXT_CAL_EN) {
424 data = set_field(data, trim_sys_gpcpll_dvfs1_dfs_ctrl_m(), 426 data = set_field(data, trim_sys_gpcpll_dvfs1_dfs_ctrl_m(),
425 trim_sys_gpcpll_dvfs1_dfs_ctrl_f( 427 trim_sys_gpcpll_dvfs1_dfs_ctrl_f(
426 DFS_EXT_CAL_EN | DFS_TESTOUT_DET)); 428 ctrl | DFS_EXT_CAL_EN | DFS_TESTOUT_DET));
427 gk20a_writel(g, trim_sys_gpcpll_dvfs1_r(), data); 429 gk20a_writel(g, trim_sys_gpcpll_dvfs1_r(), data);
428 } 430 }
429} 431}
@@ -472,6 +474,14 @@ static int clk_enbale_pll_dvfs(struct gk20a *g)
472 gk20a_writel(g, trim_sys_gpcpll_cfg3_r(), data); 474 gk20a_writel(g, trim_sys_gpcpll_cfg3_r(), data);
473 } 475 }
474 476
477 /* Set NA mode DFS control */
478 if (p->dfs_ctrl) {
479 data = gk20a_readl(g, trim_sys_gpcpll_dvfs1_r());
480 data = set_field(data, trim_sys_gpcpll_dvfs1_dfs_ctrl_m(),
481 trim_sys_gpcpll_dvfs1_dfs_ctrl_f(p->dfs_ctrl));
482 gk20a_writel(g, trim_sys_gpcpll_dvfs1_r(), data);
483 }
484
475 /* 485 /*
476 * If calibration parameters are known (either from fuses, or from 486 * If calibration parameters are known (either from fuses, or from
477 * internal calibration on boot) - use them. Internal calibration is 487 * internal calibration on boot) - use them. Internal calibration is