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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r--drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h16
-rw-r--r--drivers/gpu/nvgpu/gm20b/mm_gm20b.c26
2 files changed, 42 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
index a941eb59..4a712394 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
@@ -3562,6 +3562,10 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_r(void)
3562{ 3562{
3563 return 0x004188b0; 3563 return 0x004188b0;
3564} 3564}
3565static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_m(void)
3566{
3567 return 0x1 << 16;
3568}
3565static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r) 3569static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_v(u32 r)
3566{ 3570{
3567 return (r >> 16) & 0x1; 3571 return (r >> 16) & 0x1;
@@ -3570,6 +3574,18 @@ static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(void)
3570{ 3574{
3571 return 0x00000001; 3575 return 0x00000001;
3572} 3576}
3577static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(void)
3578{
3579 return 0x10000;
3580}
3581static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_v(void)
3582{
3583 return 0x00000000;
3584}
3585static inline u32 gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(void)
3586{
3587 return 0x0;
3588}
3573static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void) 3589static inline u32 gr_gpcs_pri_mmu_debug_wr_r(void)
3574{ 3590{
3575 return 0x004188b4; 3591 return 0x004188b4;
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
index 3d75a631..9fdd860b 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
@@ -78,6 +78,31 @@ static bool gm20b_mm_mmu_debug_mode_enabled(struct gk20a *g)
78 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(); 78 gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v();
79} 79}
80 80
81static void gm20b_mm_mmu_set_debug_mode(struct gk20a *g, bool enable)
82{
83 u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl;
84
85 if (enable) {
86 fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f();
87 gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f();
88 g->mmu_debug_ctrl = true;
89 } else {
90 fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f();
91 gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f();
92 g->mmu_debug_ctrl = false;
93 }
94
95 reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r());
96 reg_val = set_field(reg_val,
97 fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl);
98 gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val);
99
100 reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r());
101 reg_val = set_field(reg_val,
102 gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl);
103 gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val);
104}
105
81static void gm20b_mm_set_big_page_size(struct gk20a *g, 106static void gm20b_mm_set_big_page_size(struct gk20a *g,
82 void *inst_ptr, int size) 107 void *inst_ptr, int size)
83{ 108{
@@ -112,6 +137,7 @@ void gm20b_init_mm(struct gpu_ops *gops)
112{ 137{
113 gops->mm.support_sparse = gm20b_mm_support_sparse; 138 gops->mm.support_sparse = gm20b_mm_support_sparse;
114 gops->mm.is_debug_mode_enabled = gm20b_mm_mmu_debug_mode_enabled; 139 gops->mm.is_debug_mode_enabled = gm20b_mm_mmu_debug_mode_enabled;
140 gops->mm.set_debug_mode = gm20b_mm_mmu_set_debug_mode;
115 gops->mm.gmmu_map = gk20a_locked_gmmu_map; 141 gops->mm.gmmu_map = gk20a_locked_gmmu_map;
116 gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap; 142 gops->mm.gmmu_unmap = gk20a_locked_gmmu_unmap;
117 gops->mm.vm_remove = gk20a_vm_remove_support; 143 gops->mm.vm_remove = gk20a_vm_remove_support;