diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 3 |
3 files changed, 38 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 15612995..35a7a9e1 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Fifo | 2 | * GM20B Fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -223,3 +223,34 @@ void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch) | |||
223 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); | 223 | nvgpu_rwsem_up_read(&tsg->ch_list_lock); |
224 | } | 224 | } |
225 | } | 225 | } |
226 | |||
227 | static const char * const gm20b_gpc_client_descs[] = { | ||
228 | "l1 0", "t1 0", "pe 0", | ||
229 | "l1 1", "t1 1", "pe 1", | ||
230 | "l1 2", "t1 2", "pe 2", | ||
231 | "l1 3", "t1 3", "pe 3", | ||
232 | "rast", "gcc", "gpccs", | ||
233 | "prop 0", "prop 1", "prop 2", "prop 3", | ||
234 | "l1 4", "t1 4", "pe 4", | ||
235 | "l1 5", "t1 5", "pe 5", | ||
236 | "l1 6", "t1 6", "pe 6", | ||
237 | "l1 7", "t1 7", "pe 7", | ||
238 | "l1 9", "t1 9", "pe 9", | ||
239 | "l1 10", "t1 10", "pe 10", | ||
240 | "l1 11", "t1 11", "pe 11", | ||
241 | "unknown", "unknown", "unknown", "unknown", | ||
242 | "tpccs 0", "tpccs 1", "tpccs 2", | ||
243 | "tpccs 3", "tpccs 4", "tpccs 5", | ||
244 | "tpccs 6", "tpccs 7", "tpccs 8", | ||
245 | "tpccs 9", "tpccs 10", "tpccs 11", | ||
246 | }; | ||
247 | |||
248 | void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault) | ||
249 | { | ||
250 | if (mmfault->client_id >= ARRAY_SIZE(gm20b_gpc_client_descs)) | ||
251 | WARN_ON(mmfault->client_id >= | ||
252 | ARRAY_SIZE(gm20b_gpc_client_descs)); | ||
253 | else | ||
254 | mmfault->client_id_desc = | ||
255 | gm20b_gpc_client_descs[mmfault->client_id]; | ||
256 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h index 8d487358..f9e1f95d 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B Fifo | 2 | * GM20B Fifo |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -25,6 +25,7 @@ | |||
25 | #ifndef _NVHOST_GM20B_FIFO | 25 | #ifndef _NVHOST_GM20B_FIFO |
26 | #define _NVHOST_GM20B_FIFO | 26 | #define _NVHOST_GM20B_FIFO |
27 | struct gk20a; | 27 | struct gk20a; |
28 | struct mmu_fault_info; | ||
28 | 29 | ||
29 | void channel_gm20b_bind(struct channel_gk20a *c); | 30 | void channel_gm20b_bind(struct channel_gk20a *c); |
30 | void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, | 31 | void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, |
@@ -35,5 +36,6 @@ void gm20b_device_info_data_parse(struct gk20a *g, | |||
35 | u32 *pri_base, u32 *fault_id); | 36 | u32 *pri_base, u32 *fault_id); |
36 | void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); | 37 | void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); |
37 | void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch); | 38 | void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch); |
39 | void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault); | ||
38 | 40 | ||
39 | #endif | 41 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 76837ab7..328c1c38 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -416,6 +416,9 @@ static const struct gpu_ops gm20b_ops = { | |||
416 | .update_runlist = gk20a_fifo_update_runlist, | 416 | .update_runlist = gk20a_fifo_update_runlist, |
417 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | 417 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, |
418 | .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info, | 418 | .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info, |
419 | .get_mmu_fault_desc = gk20a_fifo_get_mmu_fault_desc, | ||
420 | .get_mmu_fault_client_desc = gk20a_fifo_get_mmu_fault_client_desc, | ||
421 | .get_mmu_fault_gpc_desc = gm20b_fifo_get_mmu_fault_gpc_desc, | ||
419 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | 422 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, |
420 | .get_num_fifos = gm20b_fifo_get_num_fifos, | 423 | .get_num_fifos = gm20b_fifo_get_num_fifos, |
421 | .get_pbdma_signature = gk20a_fifo_get_pbdma_signature, | 424 | .get_pbdma_signature = gk20a_fifo_get_pbdma_signature, |