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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/mm_gm20b.h')
-rw-r--r--drivers/gpu/nvgpu/gm20b/mm_gm20b.h43
1 files changed, 43 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h
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+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h
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1/*
2 * GM20B GMMU
3 *
4 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _NVHOST_GM20B_MM
26#define _NVHOST_GM20B_MM
27struct gk20a;
28
29#define PDE_ADDR_START(x, y) ((x) & ~((0x1UL << (y)) - 1))
30#define PDE_ADDR_END(x, y) ((x) | ((0x1UL << (y)) - 1))
31
32void gm20b_mm_set_big_page_size(struct gk20a *g,
33 struct nvgpu_mem *mem, int size);
34u32 gm20b_mm_get_big_page_sizes(void);
35u32 gm20b_mm_get_default_big_page_size(void);
36bool gm20b_mm_support_sparse(struct gk20a *g);
37bool gm20b_mm_is_bar1_supported(struct gk20a *g);
38int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g);
39u64 gm20b_gpu_phys_addr(struct gk20a *g,
40 struct nvgpu_gmmu_attrs *attrs, u64 phys);
41u32 gm20b_get_kind_invalid(void);
42u32 gm20b_get_kind_pitch(void);
43#endif