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path: root/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/ltc_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/ltc_gm20b.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
index dcb65372..66cd49e7 100644
--- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
@@ -61,7 +61,7 @@ int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
61 61
62 int err; 62 int err;
63 63
64 gk20a_dbg_fn(""); 64 nvgpu_log_fn(g, " ");
65 65
66 if (max_comptag_lines == 0U) 66 if (max_comptag_lines == 0U)
67 return 0; 67 return 0;
@@ -87,9 +87,9 @@ int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr)
87 if (max_comptag_lines > hw_max_comptag_lines) 87 if (max_comptag_lines > hw_max_comptag_lines)
88 max_comptag_lines = hw_max_comptag_lines; 88 max_comptag_lines = hw_max_comptag_lines;
89 89
90 gk20a_dbg_info("compbit backing store size : %d", 90 nvgpu_log_info(g, "compbit backing store size : %d",
91 compbit_backing_size); 91 compbit_backing_size);
92 gk20a_dbg_info("max comptag lines : %d", 92 nvgpu_log_info(g, "max comptag lines : %d",
93 max_comptag_lines); 93 max_comptag_lines);
94 94
95 err = nvgpu_ltc_alloc_cbc(g, compbit_backing_size); 95 err = nvgpu_ltc_alloc_cbc(g, compbit_backing_size);
@@ -121,7 +121,7 @@ int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
121 u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); 121 u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
122 const u32 max_lines = 16384U; 122 const u32 max_lines = 16384U;
123 123
124 gk20a_dbg_fn(""); 124 nvgpu_log_fn(g, " ");
125 125
126 trace_gk20a_ltc_cbc_ctrl_start(g->name, op, min, max); 126 trace_gk20a_ltc_cbc_ctrl_start(g->name, op, min, max);
127 127
@@ -134,7 +134,7 @@ int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op,
134 134
135 nvgpu_mutex_acquire(&g->mm.l2_op_lock); 135 nvgpu_mutex_acquire(&g->mm.l2_op_lock);
136 136
137 gk20a_dbg_info("clearing CBC lines %u..%u", min, iter_max); 137 nvgpu_log_info(g, "clearing CBC lines %u..%u", min, iter_max);
138 138
139 if (op == gk20a_cbc_op_clear) { 139 if (op == gk20a_cbc_op_clear) {
140 gk20a_writel( 140 gk20a_writel(
@@ -205,11 +205,11 @@ void gm20b_ltc_init_fs_state(struct gk20a *g)
205{ 205{
206 u32 reg; 206 u32 reg;
207 207
208 gk20a_dbg_info("initialize gm20b l2"); 208 nvgpu_log_info(g, "initialize gm20b l2");
209 209
210 g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r()); 210 g->max_ltc_count = gk20a_readl(g, top_num_ltcs_r());
211 g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r()); 211 g->ltc_count = gk20a_readl(g, pri_ringmaster_enum_ltc_r());
212 gk20a_dbg_info("%d ltcs out of %d", g->ltc_count, g->max_ltc_count); 212 nvgpu_log_info(g, "%d ltcs out of %d", g->ltc_count, g->max_ltc_count);
213 213
214 gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(), 214 gk20a_writel(g, ltc_ltcs_ltss_cbc_num_active_ltcs_r(),
215 g->ltc_count); 215 g->ltc_count);
@@ -459,7 +459,7 @@ void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
459 gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(), 459 gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(),
460 compbit_base_post_divide); 460 compbit_base_post_divide);
461 461
462 gk20a_dbg(gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte, 462 nvgpu_log(g, gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte,
463 "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n", 463 "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n",
464 (u32)(compbit_store_iova >> 32), 464 (u32)(compbit_store_iova >> 32),
465 (u32)(compbit_store_iova & 0xffffffff), 465 (u32)(compbit_store_iova & 0xffffffff),