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path: root/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/ltc_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/ltc_gm20b.c26
1 files changed, 9 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
index 5e938141..6fef01ea 100644
--- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
@@ -437,25 +437,17 @@ void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
437 437
438} 438}
439 439
440#ifdef CONFIG_DEBUG_FS 440void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled)
441void gm20b_ltc_sync_debugfs(struct gk20a *g)
442{ 441{
443 u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); 442 u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f();
443 u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r());
444 444
445 nvgpu_spinlock_acquire(&g->debugfs_lock); 445 if (enabled)
446 if (g->mm.ltc_enabled != g->mm.ltc_enabled_debug) { 446 /* bypass disabled (normal caching ops)*/
447 u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); 447 reg &= ~reg_f;
448 448 else
449 if (g->mm.ltc_enabled_debug) 449 /* bypass enabled (no caching) */
450 /* bypass disabled (normal caching ops)*/ 450 reg |= reg_f;
451 reg &= ~reg_f;
452 else
453 /* bypass enabled (no caching) */
454 reg |= reg_f;
455 451
456 gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); 452 gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg);
457 g->mm.ltc_enabled = g->mm.ltc_enabled_debug;
458 }
459 nvgpu_spinlock_release(&g->debugfs_lock);
460} 453}
461#endif