summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h')
-rw-r--r--drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h30
1 files changed, 27 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
index 4a712394..05f6cae5 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h
@@ -3130,15 +3130,15 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void)
3130{ 3130{
3131 return 0x0; 3131 return 0x0;
3132} 3132}
3133static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) 3133static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_0_r(void)
3134{ 3134{
3135 return 0x00504614; 3135 return 0x00504614;
3136} 3136}
3137static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) 3137static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_0_r(void)
3138{ 3138{
3139 return 0x00504624; 3139 return 0x00504624;
3140} 3140}
3141static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) 3141static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_0_r(void)
3142{ 3142{
3143 return 0x00504634; 3143 return 0x00504634;
3144} 3144}
@@ -3150,6 +3150,18 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(vo
3150{ 3150{
3151 return 0x00000000; 3151 return 0x00000000;
3152} 3152}
3153static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_2_r(void)
3154{
3155 return 0x0050461c;
3156}
3157static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_2_r(void)
3158{
3159 return 0x00504750;
3160}
3161static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_2_r(void)
3162{
3163 return 0x00504758;
3164}
3153static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) 3165static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void)
3154{ 3166{
3155 return 0x0050460c; 3167 return 0x0050460c;
@@ -3626,6 +3638,18 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void)
3626{ 3638{
3627 return 0x0; 3639 return 0x0;
3628} 3640}
3641static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void)
3642{
3643 return 0x00504614;
3644}
3645static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void)
3646{
3647 return 0x00504624;
3648}
3649static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void)
3650{
3651 return 0x00504634;
3652}
3629static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) 3653static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void)
3630{ 3654{
3631 return 0x1 << 30; 3655 return 0x1 << 30;