diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index b796e2d3..73861c07 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -954,10 +954,22 @@ static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) | |||
954 | { | 954 | { |
955 | return (v & 0x1) << 18; | 955 | return (v & 0x1) << 18; |
956 | } | 956 | } |
957 | static inline u32 gr_fecs_host_int_status_ctxsw_intr_f(u32 v) | ||
958 | { | ||
959 | return (v & 0xffff) << 0; | ||
960 | } | ||
957 | static inline u32 gr_fecs_host_int_clear_r(void) | 961 | static inline u32 gr_fecs_host_int_clear_r(void) |
958 | { | 962 | { |
959 | return 0x00409c20; | 963 | return 0x00409c20; |
960 | } | 964 | } |
965 | static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_f(u32 v) | ||
966 | { | ||
967 | return (v & 0x1) << 1; | ||
968 | } | ||
969 | static inline u32 gr_fecs_host_int_clear_ctxsw_intr1_clear_f(void) | ||
970 | { | ||
971 | return 0x2; | ||
972 | } | ||
961 | static inline u32 gr_fecs_host_int_enable_r(void) | 973 | static inline u32 gr_fecs_host_int_enable_r(void) |
962 | { | 974 | { |
963 | return 0x00409c24; | 975 | return 0x00409c24; |
@@ -3138,6 +3150,14 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_disable_f(void) | |||
3138 | { | 3150 | { |
3139 | return 0x0; | 3151 | return 0x0; |
3140 | } | 3152 | } |
3153 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_enable_f(void) | ||
3154 | { | ||
3155 | return 0x8; | ||
3156 | } | ||
3157 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_single_step_mode_disable_f(void) | ||
3158 | { | ||
3159 | return 0x0; | ||
3160 | } | ||
3141 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | 3161 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) |
3142 | { | 3162 | { |
3143 | return 0x40000000; | 3163 | return 0x40000000; |
@@ -3234,6 +3254,26 @@ static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_single_step_complete_pending_f( | |||
3234 | { | 3254 | { |
3235 | return 0x40; | 3255 | return 0x40; |
3236 | } | 3256 | } |
3257 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) | ||
3258 | { | ||
3259 | return 0x1; | ||
3260 | } | ||
3261 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_l1_error_pending_f(void) | ||
3262 | { | ||
3263 | return 0x2; | ||
3264 | } | ||
3265 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3266 | { | ||
3267 | return 0x4; | ||
3268 | } | ||
3269 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) | ||
3270 | { | ||
3271 | return 0x8; | ||
3272 | } | ||
3273 | static inline u32 gr_gpcs_tpcs_sm_hww_global_esr_timeout_error_pending_f(void) | ||
3274 | { | ||
3275 | return 0x80000000; | ||
3276 | } | ||
3237 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) | 3277 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_r(void) |
3238 | { | 3278 | { |
3239 | return 0x00504650; | 3279 | return 0x00504650; |
@@ -3250,6 +3290,26 @@ static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_single_step_complete_pending_f( | |||
3250 | { | 3290 | { |
3251 | return 0x40; | 3291 | return 0x40; |
3252 | } | 3292 | } |
3293 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_sm_to_sm_fault_pending_f(void) | ||
3294 | { | ||
3295 | return 0x1; | ||
3296 | } | ||
3297 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_l1_error_pending_f(void) | ||
3298 | { | ||
3299 | return 0x2; | ||
3300 | } | ||
3301 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_multiple_warp_errors_pending_f(void) | ||
3302 | { | ||
3303 | return 0x4; | ||
3304 | } | ||
3305 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_physical_stack_overflow_error_pending_f(void) | ||
3306 | { | ||
3307 | return 0x8; | ||
3308 | } | ||
3309 | static inline u32 gr_gpc0_tpc0_sm_hww_global_esr_timeout_error_pending_f(void) | ||
3310 | { | ||
3311 | return 0x80000000; | ||
3312 | } | ||
3253 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) | 3313 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_r(void) |
3254 | { | 3314 | { |
3255 | return 0x00504224; | 3315 | return 0x00504224; |
@@ -3694,6 +3754,18 @@ static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_stop_trigger_disable_f(void) | |||
3694 | { | 3754 | { |
3695 | return 0x0; | 3755 | return 0x0; |
3696 | } | 3756 | } |
3757 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_m(void) | ||
3758 | { | ||
3759 | return 0x1 << 3; | ||
3760 | } | ||
3761 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_enable_f(void) | ||
3762 | { | ||
3763 | return 0x8; | ||
3764 | } | ||
3765 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_single_step_mode_disable_f(void) | ||
3766 | { | ||
3767 | return 0x0; | ||
3768 | } | ||
3697 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) | 3769 | static inline u32 gr_gpcs_tpcs_sm_dbgr_control0_run_trigger_m(void) |
3698 | { | 3770 | { |
3699 | return 0x1 << 30; | 3771 | return 0x1 << 30; |