diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h | 561 |
1 files changed, 0 insertions, 561 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h deleted file mode 100644 index 964f4bf9..00000000 --- a/drivers/gpu/nvgpu/gm20b/hw_fifo_gm20b.h +++ /dev/null | |||
@@ -1,561 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_fifo_gm20b_h_ | ||
51 | #define _hw_fifo_gm20b_h_ | ||
52 | |||
53 | static inline u32 fifo_bar1_base_r(void) | ||
54 | { | ||
55 | return 0x00002254; | ||
56 | } | ||
57 | static inline u32 fifo_bar1_base_ptr_f(u32 v) | ||
58 | { | ||
59 | return (v & 0xfffffff) << 0; | ||
60 | } | ||
61 | static inline u32 fifo_bar1_base_ptr_align_shift_v(void) | ||
62 | { | ||
63 | return 0x0000000c; | ||
64 | } | ||
65 | static inline u32 fifo_bar1_base_valid_false_f(void) | ||
66 | { | ||
67 | return 0x0; | ||
68 | } | ||
69 | static inline u32 fifo_bar1_base_valid_true_f(void) | ||
70 | { | ||
71 | return 0x10000000; | ||
72 | } | ||
73 | static inline u32 fifo_runlist_base_r(void) | ||
74 | { | ||
75 | return 0x00002270; | ||
76 | } | ||
77 | static inline u32 fifo_runlist_base_ptr_f(u32 v) | ||
78 | { | ||
79 | return (v & 0xfffffff) << 0; | ||
80 | } | ||
81 | static inline u32 fifo_runlist_base_target_vid_mem_f(void) | ||
82 | { | ||
83 | return 0x0; | ||
84 | } | ||
85 | static inline u32 fifo_runlist_base_target_sys_mem_coh_f(void) | ||
86 | { | ||
87 | return 0x20000000; | ||
88 | } | ||
89 | static inline u32 fifo_runlist_base_target_sys_mem_ncoh_f(void) | ||
90 | { | ||
91 | return 0x30000000; | ||
92 | } | ||
93 | static inline u32 fifo_runlist_r(void) | ||
94 | { | ||
95 | return 0x00002274; | ||
96 | } | ||
97 | static inline u32 fifo_runlist_engine_f(u32 v) | ||
98 | { | ||
99 | return (v & 0xf) << 20; | ||
100 | } | ||
101 | static inline u32 fifo_eng_runlist_base_r(u32 i) | ||
102 | { | ||
103 | return 0x00002280 + i*8; | ||
104 | } | ||
105 | static inline u32 fifo_eng_runlist_base__size_1_v(void) | ||
106 | { | ||
107 | return 0x00000001; | ||
108 | } | ||
109 | static inline u32 fifo_eng_runlist_r(u32 i) | ||
110 | { | ||
111 | return 0x00002284 + i*8; | ||
112 | } | ||
113 | static inline u32 fifo_eng_runlist__size_1_v(void) | ||
114 | { | ||
115 | return 0x00000001; | ||
116 | } | ||
117 | static inline u32 fifo_eng_runlist_length_f(u32 v) | ||
118 | { | ||
119 | return (v & 0xffff) << 0; | ||
120 | } | ||
121 | static inline u32 fifo_eng_runlist_length_max_v(void) | ||
122 | { | ||
123 | return 0x0000ffff; | ||
124 | } | ||
125 | static inline u32 fifo_eng_runlist_pending_true_f(void) | ||
126 | { | ||
127 | return 0x100000; | ||
128 | } | ||
129 | static inline u32 fifo_pb_timeslice_r(u32 i) | ||
130 | { | ||
131 | return 0x00002350 + i*4; | ||
132 | } | ||
133 | static inline u32 fifo_pb_timeslice_timeout_16_f(void) | ||
134 | { | ||
135 | return 0x10; | ||
136 | } | ||
137 | static inline u32 fifo_pb_timeslice_timescale_0_f(void) | ||
138 | { | ||
139 | return 0x0; | ||
140 | } | ||
141 | static inline u32 fifo_pb_timeslice_enable_true_f(void) | ||
142 | { | ||
143 | return 0x10000000; | ||
144 | } | ||
145 | static inline u32 fifo_pbdma_map_r(u32 i) | ||
146 | { | ||
147 | return 0x00002390 + i*4; | ||
148 | } | ||
149 | static inline u32 fifo_intr_0_r(void) | ||
150 | { | ||
151 | return 0x00002100; | ||
152 | } | ||
153 | static inline u32 fifo_intr_0_bind_error_pending_f(void) | ||
154 | { | ||
155 | return 0x1; | ||
156 | } | ||
157 | static inline u32 fifo_intr_0_bind_error_reset_f(void) | ||
158 | { | ||
159 | return 0x1; | ||
160 | } | ||
161 | static inline u32 fifo_intr_0_sched_error_pending_f(void) | ||
162 | { | ||
163 | return 0x100; | ||
164 | } | ||
165 | static inline u32 fifo_intr_0_sched_error_reset_f(void) | ||
166 | { | ||
167 | return 0x100; | ||
168 | } | ||
169 | static inline u32 fifo_intr_0_chsw_error_pending_f(void) | ||
170 | { | ||
171 | return 0x10000; | ||
172 | } | ||
173 | static inline u32 fifo_intr_0_chsw_error_reset_f(void) | ||
174 | { | ||
175 | return 0x10000; | ||
176 | } | ||
177 | static inline u32 fifo_intr_0_fb_flush_timeout_pending_f(void) | ||
178 | { | ||
179 | return 0x800000; | ||
180 | } | ||
181 | static inline u32 fifo_intr_0_fb_flush_timeout_reset_f(void) | ||
182 | { | ||
183 | return 0x800000; | ||
184 | } | ||
185 | static inline u32 fifo_intr_0_lb_error_pending_f(void) | ||
186 | { | ||
187 | return 0x1000000; | ||
188 | } | ||
189 | static inline u32 fifo_intr_0_lb_error_reset_f(void) | ||
190 | { | ||
191 | return 0x1000000; | ||
192 | } | ||
193 | static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) | ||
194 | { | ||
195 | return 0x8000000; | ||
196 | } | ||
197 | static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) | ||
198 | { | ||
199 | return 0x8000000; | ||
200 | } | ||
201 | static inline u32 fifo_intr_0_mmu_fault_pending_f(void) | ||
202 | { | ||
203 | return 0x10000000; | ||
204 | } | ||
205 | static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) | ||
206 | { | ||
207 | return 0x20000000; | ||
208 | } | ||
209 | static inline u32 fifo_intr_0_runlist_event_pending_f(void) | ||
210 | { | ||
211 | return 0x40000000; | ||
212 | } | ||
213 | static inline u32 fifo_intr_0_channel_intr_pending_f(void) | ||
214 | { | ||
215 | return 0x80000000; | ||
216 | } | ||
217 | static inline u32 fifo_intr_en_0_r(void) | ||
218 | { | ||
219 | return 0x00002140; | ||
220 | } | ||
221 | static inline u32 fifo_intr_en_0_sched_error_f(u32 v) | ||
222 | { | ||
223 | return (v & 0x1) << 8; | ||
224 | } | ||
225 | static inline u32 fifo_intr_en_0_sched_error_m(void) | ||
226 | { | ||
227 | return 0x1 << 8; | ||
228 | } | ||
229 | static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) | ||
230 | { | ||
231 | return (v & 0x1) << 28; | ||
232 | } | ||
233 | static inline u32 fifo_intr_en_0_mmu_fault_m(void) | ||
234 | { | ||
235 | return 0x1 << 28; | ||
236 | } | ||
237 | static inline u32 fifo_intr_en_1_r(void) | ||
238 | { | ||
239 | return 0x00002528; | ||
240 | } | ||
241 | static inline u32 fifo_intr_bind_error_r(void) | ||
242 | { | ||
243 | return 0x0000252c; | ||
244 | } | ||
245 | static inline u32 fifo_intr_sched_error_r(void) | ||
246 | { | ||
247 | return 0x0000254c; | ||
248 | } | ||
249 | static inline u32 fifo_intr_sched_error_code_f(u32 v) | ||
250 | { | ||
251 | return (v & 0xff) << 0; | ||
252 | } | ||
253 | static inline u32 fifo_intr_sched_error_code_ctxsw_timeout_v(void) | ||
254 | { | ||
255 | return 0x0000000a; | ||
256 | } | ||
257 | static inline u32 fifo_intr_chsw_error_r(void) | ||
258 | { | ||
259 | return 0x0000256c; | ||
260 | } | ||
261 | static inline u32 fifo_intr_mmu_fault_id_r(void) | ||
262 | { | ||
263 | return 0x0000259c; | ||
264 | } | ||
265 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) | ||
266 | { | ||
267 | return 0x00000000; | ||
268 | } | ||
269 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) | ||
270 | { | ||
271 | return 0x0; | ||
272 | } | ||
273 | static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) | ||
274 | { | ||
275 | return 0x00002800 + i*16; | ||
276 | } | ||
277 | static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) | ||
278 | { | ||
279 | return (r >> 0) & 0xfffffff; | ||
280 | } | ||
281 | static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) | ||
282 | { | ||
283 | return 0x0000000c; | ||
284 | } | ||
285 | static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) | ||
286 | { | ||
287 | return 0x00002804 + i*16; | ||
288 | } | ||
289 | static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) | ||
290 | { | ||
291 | return 0x00002808 + i*16; | ||
292 | } | ||
293 | static inline u32 fifo_intr_mmu_fault_info_r(u32 i) | ||
294 | { | ||
295 | return 0x0000280c + i*16; | ||
296 | } | ||
297 | static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) | ||
298 | { | ||
299 | return (r >> 0) & 0xf; | ||
300 | } | ||
301 | static inline u32 fifo_intr_mmu_fault_info_engine_subid_v(u32 r) | ||
302 | { | ||
303 | return (r >> 6) & 0x1; | ||
304 | } | ||
305 | static inline u32 fifo_intr_mmu_fault_info_engine_subid_gpc_v(void) | ||
306 | { | ||
307 | return 0x00000000; | ||
308 | } | ||
309 | static inline u32 fifo_intr_mmu_fault_info_engine_subid_hub_v(void) | ||
310 | { | ||
311 | return 0x00000001; | ||
312 | } | ||
313 | static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) | ||
314 | { | ||
315 | return (r >> 8) & 0x3f; | ||
316 | } | ||
317 | static inline u32 fifo_intr_pbdma_id_r(void) | ||
318 | { | ||
319 | return 0x000025a0; | ||
320 | } | ||
321 | static inline u32 fifo_intr_pbdma_id_status_f(u32 v, u32 i) | ||
322 | { | ||
323 | return (v & 0x1) << (0 + i*1); | ||
324 | } | ||
325 | static inline u32 fifo_intr_pbdma_id_status_v(u32 r, u32 i) | ||
326 | { | ||
327 | return (r >> (0 + i*1)) & 0x1; | ||
328 | } | ||
329 | static inline u32 fifo_intr_pbdma_id_status__size_1_v(void) | ||
330 | { | ||
331 | return 0x00000001; | ||
332 | } | ||
333 | static inline u32 fifo_intr_runlist_r(void) | ||
334 | { | ||
335 | return 0x00002a00; | ||
336 | } | ||
337 | static inline u32 fifo_fb_timeout_r(void) | ||
338 | { | ||
339 | return 0x00002a04; | ||
340 | } | ||
341 | static inline u32 fifo_fb_timeout_period_m(void) | ||
342 | { | ||
343 | return 0x3fffffff << 0; | ||
344 | } | ||
345 | static inline u32 fifo_fb_timeout_period_max_f(void) | ||
346 | { | ||
347 | return 0x3fffffff; | ||
348 | } | ||
349 | static inline u32 fifo_error_sched_disable_r(void) | ||
350 | { | ||
351 | return 0x0000262c; | ||
352 | } | ||
353 | static inline u32 fifo_sched_disable_r(void) | ||
354 | { | ||
355 | return 0x00002630; | ||
356 | } | ||
357 | static inline u32 fifo_sched_disable_runlist_f(u32 v, u32 i) | ||
358 | { | ||
359 | return (v & 0x1) << (0 + i*1); | ||
360 | } | ||
361 | static inline u32 fifo_sched_disable_runlist_m(u32 i) | ||
362 | { | ||
363 | return 0x1 << (0 + i*1); | ||
364 | } | ||
365 | static inline u32 fifo_sched_disable_true_v(void) | ||
366 | { | ||
367 | return 0x00000001; | ||
368 | } | ||
369 | static inline u32 fifo_preempt_r(void) | ||
370 | { | ||
371 | return 0x00002634; | ||
372 | } | ||
373 | static inline u32 fifo_preempt_pending_true_f(void) | ||
374 | { | ||
375 | return 0x100000; | ||
376 | } | ||
377 | static inline u32 fifo_preempt_type_channel_f(void) | ||
378 | { | ||
379 | return 0x0; | ||
380 | } | ||
381 | static inline u32 fifo_preempt_type_tsg_f(void) | ||
382 | { | ||
383 | return 0x1000000; | ||
384 | } | ||
385 | static inline u32 fifo_preempt_chid_f(u32 v) | ||
386 | { | ||
387 | return (v & 0xfff) << 0; | ||
388 | } | ||
389 | static inline u32 fifo_preempt_id_f(u32 v) | ||
390 | { | ||
391 | return (v & 0xfff) << 0; | ||
392 | } | ||
393 | static inline u32 fifo_trigger_mmu_fault_r(u32 i) | ||
394 | { | ||
395 | return 0x00002a30 + i*4; | ||
396 | } | ||
397 | static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) | ||
398 | { | ||
399 | return (v & 0x1f) << 0; | ||
400 | } | ||
401 | static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) | ||
402 | { | ||
403 | return (v & 0x1) << 8; | ||
404 | } | ||
405 | static inline u32 fifo_engine_status_r(u32 i) | ||
406 | { | ||
407 | return 0x00002640 + i*8; | ||
408 | } | ||
409 | static inline u32 fifo_engine_status__size_1_v(void) | ||
410 | { | ||
411 | return 0x00000002; | ||
412 | } | ||
413 | static inline u32 fifo_engine_status_id_v(u32 r) | ||
414 | { | ||
415 | return (r >> 0) & 0xfff; | ||
416 | } | ||
417 | static inline u32 fifo_engine_status_id_type_v(u32 r) | ||
418 | { | ||
419 | return (r >> 12) & 0x1; | ||
420 | } | ||
421 | static inline u32 fifo_engine_status_id_type_chid_v(void) | ||
422 | { | ||
423 | return 0x00000000; | ||
424 | } | ||
425 | static inline u32 fifo_engine_status_id_type_tsgid_v(void) | ||
426 | { | ||
427 | return 0x00000001; | ||
428 | } | ||
429 | static inline u32 fifo_engine_status_ctx_status_v(u32 r) | ||
430 | { | ||
431 | return (r >> 13) & 0x7; | ||
432 | } | ||
433 | static inline u32 fifo_engine_status_ctx_status_invalid_v(void) | ||
434 | { | ||
435 | return 0x00000000; | ||
436 | } | ||
437 | static inline u32 fifo_engine_status_ctx_status_valid_v(void) | ||
438 | { | ||
439 | return 0x00000001; | ||
440 | } | ||
441 | static inline u32 fifo_engine_status_ctx_status_ctxsw_load_v(void) | ||
442 | { | ||
443 | return 0x00000005; | ||
444 | } | ||
445 | static inline u32 fifo_engine_status_ctx_status_ctxsw_save_v(void) | ||
446 | { | ||
447 | return 0x00000006; | ||
448 | } | ||
449 | static inline u32 fifo_engine_status_ctx_status_ctxsw_switch_v(void) | ||
450 | { | ||
451 | return 0x00000007; | ||
452 | } | ||
453 | static inline u32 fifo_engine_status_next_id_v(u32 r) | ||
454 | { | ||
455 | return (r >> 16) & 0xfff; | ||
456 | } | ||
457 | static inline u32 fifo_engine_status_next_id_type_v(u32 r) | ||
458 | { | ||
459 | return (r >> 28) & 0x1; | ||
460 | } | ||
461 | static inline u32 fifo_engine_status_next_id_type_chid_v(void) | ||
462 | { | ||
463 | return 0x00000000; | ||
464 | } | ||
465 | static inline u32 fifo_engine_status_faulted_v(u32 r) | ||
466 | { | ||
467 | return (r >> 30) & 0x1; | ||
468 | } | ||
469 | static inline u32 fifo_engine_status_faulted_true_v(void) | ||
470 | { | ||
471 | return 0x00000001; | ||
472 | } | ||
473 | static inline u32 fifo_engine_status_engine_v(u32 r) | ||
474 | { | ||
475 | return (r >> 31) & 0x1; | ||
476 | } | ||
477 | static inline u32 fifo_engine_status_engine_idle_v(void) | ||
478 | { | ||
479 | return 0x00000000; | ||
480 | } | ||
481 | static inline u32 fifo_engine_status_engine_busy_v(void) | ||
482 | { | ||
483 | return 0x00000001; | ||
484 | } | ||
485 | static inline u32 fifo_engine_status_ctxsw_v(u32 r) | ||
486 | { | ||
487 | return (r >> 15) & 0x1; | ||
488 | } | ||
489 | static inline u32 fifo_engine_status_ctxsw_in_progress_v(void) | ||
490 | { | ||
491 | return 0x00000001; | ||
492 | } | ||
493 | static inline u32 fifo_engine_status_ctxsw_in_progress_f(void) | ||
494 | { | ||
495 | return 0x8000; | ||
496 | } | ||
497 | static inline u32 fifo_pbdma_status_r(u32 i) | ||
498 | { | ||
499 | return 0x00003080 + i*4; | ||
500 | } | ||
501 | static inline u32 fifo_pbdma_status__size_1_v(void) | ||
502 | { | ||
503 | return 0x00000001; | ||
504 | } | ||
505 | static inline u32 fifo_pbdma_status_id_v(u32 r) | ||
506 | { | ||
507 | return (r >> 0) & 0xfff; | ||
508 | } | ||
509 | static inline u32 fifo_pbdma_status_id_type_v(u32 r) | ||
510 | { | ||
511 | return (r >> 12) & 0x1; | ||
512 | } | ||
513 | static inline u32 fifo_pbdma_status_id_type_chid_v(void) | ||
514 | { | ||
515 | return 0x00000000; | ||
516 | } | ||
517 | static inline u32 fifo_pbdma_status_id_type_tsgid_v(void) | ||
518 | { | ||
519 | return 0x00000001; | ||
520 | } | ||
521 | static inline u32 fifo_pbdma_status_chan_status_v(u32 r) | ||
522 | { | ||
523 | return (r >> 13) & 0x7; | ||
524 | } | ||
525 | static inline u32 fifo_pbdma_status_chan_status_valid_v(void) | ||
526 | { | ||
527 | return 0x00000001; | ||
528 | } | ||
529 | static inline u32 fifo_pbdma_status_chan_status_chsw_load_v(void) | ||
530 | { | ||
531 | return 0x00000005; | ||
532 | } | ||
533 | static inline u32 fifo_pbdma_status_chan_status_chsw_save_v(void) | ||
534 | { | ||
535 | return 0x00000006; | ||
536 | } | ||
537 | static inline u32 fifo_pbdma_status_chan_status_chsw_switch_v(void) | ||
538 | { | ||
539 | return 0x00000007; | ||
540 | } | ||
541 | static inline u32 fifo_pbdma_status_next_id_v(u32 r) | ||
542 | { | ||
543 | return (r >> 16) & 0xfff; | ||
544 | } | ||
545 | static inline u32 fifo_pbdma_status_next_id_type_v(u32 r) | ||
546 | { | ||
547 | return (r >> 28) & 0x1; | ||
548 | } | ||
549 | static inline u32 fifo_pbdma_status_next_id_type_chid_v(void) | ||
550 | { | ||
551 | return 0x00000000; | ||
552 | } | ||
553 | static inline u32 fifo_pbdma_status_chsw_v(u32 r) | ||
554 | { | ||
555 | return (r >> 15) & 0x1; | ||
556 | } | ||
557 | static inline u32 fifo_pbdma_status_chsw_in_progress_v(void) | ||
558 | { | ||
559 | return 0x00000001; | ||
560 | } | ||
561 | #endif | ||