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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hal_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c708
1 files changed, 708 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
new file mode 100644
index 00000000..227b6b6c
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -0,0 +1,708 @@
1/*
2 * GM20B Graphics
3 *
4 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "gk20a/gk20a.h"
26#include "gk20a/ce2_gk20a.h"
27#include "gk20a/dbg_gpu_gk20a.h"
28#include "gk20a/fb_gk20a.h"
29#include "gk20a/fifo_gk20a.h"
30#include "gk20a/therm_gk20a.h"
31#include "gk20a/mm_gk20a.h"
32#include "gk20a/css_gr_gk20a.h"
33#include "gk20a/mc_gk20a.h"
34#include "gk20a/bus_gk20a.h"
35#include "gk20a/flcn_gk20a.h"
36#include "gk20a/priv_ring_gk20a.h"
37#include "gk20a/regops_gk20a.h"
38#include "gk20a/pmu_gk20a.h"
39#include "gk20a/gr_gk20a.h"
40#include "gk20a/tsg_gk20a.h"
41
42#include "ltc_gm20b.h"
43#include "gr_gm20b.h"
44#include "ltc_gm20b.h"
45#include "fb_gm20b.h"
46#include "gm20b_gating_reglist.h"
47#include "fifo_gm20b.h"
48#include "gr_ctx_gm20b.h"
49#include "mm_gm20b.h"
50#include "pmu_gm20b.h"
51#include "clk_gm20b.h"
52#include "regops_gm20b.h"
53#include "therm_gm20b.h"
54#include "bus_gm20b.h"
55#include "hal_gm20b.h"
56#include "acr_gm20b.h"
57
58#include <nvgpu/debug.h>
59#include <nvgpu/bug.h>
60#include <nvgpu/enabled.h>
61#include <nvgpu/bus.h>
62
63#include <nvgpu/hw/gm20b/hw_proj_gm20b.h>
64#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
65#include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
66#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
67#include <nvgpu/hw/gm20b/hw_top_gm20b.h>
68#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
69#include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
70
71#define PRIV_SECURITY_DISABLE 0x01
72
73int gm20b_get_litter_value(struct gk20a *g, int value)
74{
75 int ret = EINVAL;
76 switch (value) {
77 case GPU_LIT_NUM_GPCS:
78 ret = proj_scal_litter_num_gpcs_v();
79 break;
80 case GPU_LIT_NUM_PES_PER_GPC:
81 ret = proj_scal_litter_num_pes_per_gpc_v();
82 break;
83 case GPU_LIT_NUM_ZCULL_BANKS:
84 ret = proj_scal_litter_num_zcull_banks_v();
85 break;
86 case GPU_LIT_NUM_TPC_PER_GPC:
87 ret = proj_scal_litter_num_tpc_per_gpc_v();
88 break;
89 case GPU_LIT_NUM_SM_PER_TPC:
90 ret = proj_scal_litter_num_sm_per_tpc_v();
91 break;
92 case GPU_LIT_NUM_FBPS:
93 ret = proj_scal_litter_num_fbps_v();
94 break;
95 case GPU_LIT_GPC_BASE:
96 ret = proj_gpc_base_v();
97 break;
98 case GPU_LIT_GPC_STRIDE:
99 ret = proj_gpc_stride_v();
100 break;
101 case GPU_LIT_GPC_SHARED_BASE:
102 ret = proj_gpc_shared_base_v();
103 break;
104 case GPU_LIT_TPC_IN_GPC_BASE:
105 ret = proj_tpc_in_gpc_base_v();
106 break;
107 case GPU_LIT_TPC_IN_GPC_STRIDE:
108 ret = proj_tpc_in_gpc_stride_v();
109 break;
110 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
111 ret = proj_tpc_in_gpc_shared_base_v();
112 break;
113 case GPU_LIT_PPC_IN_GPC_BASE:
114 ret = proj_ppc_in_gpc_base_v();
115 break;
116 case GPU_LIT_PPC_IN_GPC_STRIDE:
117 ret = proj_ppc_in_gpc_stride_v();
118 break;
119 case GPU_LIT_PPC_IN_GPC_SHARED_BASE:
120 ret = proj_ppc_in_gpc_shared_base_v();
121 break;
122 case GPU_LIT_ROP_BASE:
123 ret = proj_rop_base_v();
124 break;
125 case GPU_LIT_ROP_STRIDE:
126 ret = proj_rop_stride_v();
127 break;
128 case GPU_LIT_ROP_SHARED_BASE:
129 ret = proj_rop_shared_base_v();
130 break;
131 case GPU_LIT_HOST_NUM_ENGINES:
132 ret = proj_host_num_engines_v();
133 break;
134 case GPU_LIT_HOST_NUM_PBDMA:
135 ret = proj_host_num_pbdma_v();
136 break;
137 case GPU_LIT_LTC_STRIDE:
138 ret = proj_ltc_stride_v();
139 break;
140 case GPU_LIT_LTS_STRIDE:
141 ret = proj_lts_stride_v();
142 break;
143 /* Even though GM20B doesn't have an FBPA unit, the HW reports one,
144 * and the microcode as a result leaves space in the context buffer
145 * for one, so make sure SW accounts for this also.
146 */
147 case GPU_LIT_NUM_FBPAS:
148 ret = proj_scal_litter_num_fbpas_v();
149 break;
150 /* Hardcode FBPA values other than NUM_FBPAS to 0. */
151 case GPU_LIT_FBPA_STRIDE:
152 case GPU_LIT_FBPA_BASE:
153 case GPU_LIT_FBPA_SHARED_BASE:
154 ret = 0;
155 break;
156 case GPU_LIT_TWOD_CLASS:
157 ret = FERMI_TWOD_A;
158 break;
159 case GPU_LIT_THREED_CLASS:
160 ret = MAXWELL_B;
161 break;
162 case GPU_LIT_COMPUTE_CLASS:
163 ret = MAXWELL_COMPUTE_B;
164 break;
165 case GPU_LIT_GPFIFO_CLASS:
166 ret = MAXWELL_CHANNEL_GPFIFO_A;
167 break;
168 case GPU_LIT_I2M_CLASS:
169 ret = KEPLER_INLINE_TO_MEMORY_B;
170 break;
171 case GPU_LIT_DMA_COPY_CLASS:
172 ret = MAXWELL_DMA_COPY_A;
173 break;
174 default:
175 nvgpu_err(g, "Missing definition %d", value);
176 BUG();
177 break;
178 }
179
180 return ret;
181}
182
183static const struct gpu_ops gm20b_ops = {
184 .ltc = {
185 .determine_L2_size_bytes = gm20b_determine_L2_size_bytes,
186 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
187 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
188 .init_cbc = gm20b_ltc_init_cbc,
189 .init_fs_state = gm20b_ltc_init_fs_state,
190 .init_comptags = gm20b_ltc_init_comptags,
191 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
192 .isr = gm20b_ltc_isr,
193 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
194 .flush = gm20b_flush_ltc,
195 .set_enabled = gm20b_ltc_set_enabled,
196 },
197 .ce2 = {
198 .isr_stall = gk20a_ce2_isr,
199 .isr_nonstall = gk20a_ce2_nonstall_isr,
200 },
201 .gr = {
202 .get_patch_slots = gr_gk20a_get_patch_slots,
203 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
204 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
205 .cb_size_default = gr_gm20b_cb_size_default,
206 .calc_global_ctx_buffer_size =
207 gr_gm20b_calc_global_ctx_buffer_size,
208 .commit_global_attrib_cb = gr_gm20b_commit_global_attrib_cb,
209 .commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb,
210 .commit_global_cb_manager = gr_gm20b_commit_global_cb_manager,
211 .commit_global_pagepool = gr_gm20b_commit_global_pagepool,
212 .handle_sw_method = gr_gm20b_handle_sw_method,
213 .set_alpha_circular_buffer_size =
214 gr_gm20b_set_alpha_circular_buffer_size,
215 .set_circular_buffer_size = gr_gm20b_set_circular_buffer_size,
216 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
217 .is_valid_class = gr_gm20b_is_valid_class,
218 .is_valid_gfx_class = gr_gm20b_is_valid_gfx_class,
219 .is_valid_compute_class = gr_gm20b_is_valid_compute_class,
220 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
221 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
222 .init_fs_state = gr_gm20b_init_fs_state,
223 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
224 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
225 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
226 .set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask,
227 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
228 .free_channel_ctx = gk20a_free_channel_ctx,
229 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
230 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull,
231 .get_zcull_info = gr_gk20a_get_zcull_info,
232 .is_tpc_addr = gr_gm20b_is_tpc_addr,
233 .get_tpc_num = gr_gm20b_get_tpc_num,
234 .detect_sm_arch = gr_gm20b_detect_sm_arch,
235 .add_zbc_color = gr_gk20a_add_zbc_color,
236 .add_zbc_depth = gr_gk20a_add_zbc_depth,
237 .zbc_set_table = gk20a_gr_zbc_set_table,
238 .zbc_query_table = gr_gk20a_query_zbc,
239 .pmu_save_zbc = gk20a_pmu_save_zbc,
240 .add_zbc = gr_gk20a_add_zbc,
241 .pagepool_default_size = gr_gm20b_pagepool_default_size,
242 .init_ctx_state = gr_gk20a_init_ctx_state,
243 .alloc_gr_ctx = gr_gm20b_alloc_gr_ctx,
244 .free_gr_ctx = gr_gk20a_free_gr_ctx,
245 .update_ctxsw_preemption_mode =
246 gr_gm20b_update_ctxsw_preemption_mode,
247 .dump_gr_regs = gr_gm20b_dump_gr_status_regs,
248 .update_pc_sampling = gr_gm20b_update_pc_sampling,
249 .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
250 .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp,
251 .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc,
252 .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
253 .get_max_fbps_count = gr_gm20b_get_max_fbps_count,
254 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
255 .wait_empty = gr_gk20a_wait_idle,
256 .init_cyclestats = gr_gm20b_init_cyclestats,
257 .set_sm_debug_mode = gr_gk20a_set_sm_debug_mode,
258 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
259 .bpt_reg_info = gr_gm20b_bpt_reg_info,
260 .get_access_map = gr_gm20b_get_access_map,
261 .handle_fecs_error = gk20a_gr_handle_fecs_error,
262 .handle_sm_exception = gr_gk20a_handle_sm_exception,
263 .handle_tex_exception = gr_gk20a_handle_tex_exception,
264 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
265 .enable_exceptions = gk20a_gr_enable_exceptions,
266 .get_lrf_tex_ltc_dram_override = NULL,
267 .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
268 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
269 .record_sm_error_state = gm20b_gr_record_sm_error_state,
270 .update_sm_error_state = gm20b_gr_update_sm_error_state,
271 .clear_sm_error_state = gm20b_gr_clear_sm_error_state,
272 .suspend_contexts = gr_gk20a_suspend_contexts,
273 .resume_contexts = gr_gk20a_resume_contexts,
274 .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
275 .init_sm_id_table = gr_gk20a_init_sm_id_table,
276 .load_smid_config = gr_gm20b_load_smid_config,
277 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
278 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
279 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
280 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
281 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
282 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
283 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
284 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
285 .commit_inst = gr_gk20a_commit_inst,
286 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
287 .write_pm_ptr = gr_gk20a_write_pm_ptr,
288 .init_elcg_mode = gr_gk20a_init_elcg_mode,
289 .load_tpc_mask = gr_gm20b_load_tpc_mask,
290 .inval_icache = gr_gk20a_inval_icache,
291 .trigger_suspend = gr_gk20a_trigger_suspend,
292 .wait_for_pause = gr_gk20a_wait_for_pause,
293 .resume_from_pause = gr_gk20a_resume_from_pause,
294 .clear_sm_errors = gr_gk20a_clear_sm_errors,
295 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
296 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
297 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
298 .suspend_single_sm = gk20a_gr_suspend_single_sm,
299 .suspend_all_sms = gk20a_gr_suspend_all_sms,
300 .resume_single_sm = gk20a_gr_resume_single_sm,
301 .resume_all_sms = gk20a_gr_resume_all_sms,
302 .get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr,
303 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
304 .get_sm_no_lock_down_hww_global_esr_mask =
305 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
306 .lock_down_sm = gk20a_gr_lock_down_sm,
307 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
308 .clear_sm_hww = gm20b_gr_clear_sm_hww,
309 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
310 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
311 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
312 .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data,
313 },
314 .fb = {
315 .reset = fb_gk20a_reset,
316 .init_hw = gk20a_fb_init_hw,
317 .init_fs_state = fb_gm20b_init_fs_state,
318 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
319 .set_use_full_comp_tag_line =
320 gm20b_fb_set_use_full_comp_tag_line,
321 .compression_page_size = gm20b_fb_compression_page_size,
322 .compressible_page_size = gm20b_fb_compressible_page_size,
323 .vpr_info_fetch = gm20b_fb_vpr_info_fetch,
324 .dump_vpr_wpr_info = gm20b_fb_dump_vpr_wpr_info,
325 .read_wpr_info = gm20b_fb_read_wpr_info,
326 .is_debug_mode_enabled = gm20b_fb_debug_mode_enabled,
327 .set_debug_mode = gm20b_fb_set_debug_mode,
328 .tlb_invalidate = gk20a_fb_tlb_invalidate,
329 .mem_unlock = NULL,
330 },
331 .clock_gating = {
332 .slcg_bus_load_gating_prod =
333 gm20b_slcg_bus_load_gating_prod,
334 .slcg_ce2_load_gating_prod =
335 gm20b_slcg_ce2_load_gating_prod,
336 .slcg_chiplet_load_gating_prod =
337 gm20b_slcg_chiplet_load_gating_prod,
338 .slcg_ctxsw_firmware_load_gating_prod =
339 gm20b_slcg_ctxsw_firmware_load_gating_prod,
340 .slcg_fb_load_gating_prod =
341 gm20b_slcg_fb_load_gating_prod,
342 .slcg_fifo_load_gating_prod =
343 gm20b_slcg_fifo_load_gating_prod,
344 .slcg_gr_load_gating_prod =
345 gr_gm20b_slcg_gr_load_gating_prod,
346 .slcg_ltc_load_gating_prod =
347 ltc_gm20b_slcg_ltc_load_gating_prod,
348 .slcg_perf_load_gating_prod =
349 gm20b_slcg_perf_load_gating_prod,
350 .slcg_priring_load_gating_prod =
351 gm20b_slcg_priring_load_gating_prod,
352 .slcg_pmu_load_gating_prod =
353 gm20b_slcg_pmu_load_gating_prod,
354 .slcg_therm_load_gating_prod =
355 gm20b_slcg_therm_load_gating_prod,
356 .slcg_xbar_load_gating_prod =
357 gm20b_slcg_xbar_load_gating_prod,
358 .blcg_bus_load_gating_prod =
359 gm20b_blcg_bus_load_gating_prod,
360 .blcg_ctxsw_firmware_load_gating_prod =
361 gm20b_blcg_ctxsw_firmware_load_gating_prod,
362 .blcg_fb_load_gating_prod =
363 gm20b_blcg_fb_load_gating_prod,
364 .blcg_fifo_load_gating_prod =
365 gm20b_blcg_fifo_load_gating_prod,
366 .blcg_gr_load_gating_prod =
367 gm20b_blcg_gr_load_gating_prod,
368 .blcg_ltc_load_gating_prod =
369 gm20b_blcg_ltc_load_gating_prod,
370 .blcg_pwr_csb_load_gating_prod =
371 gm20b_blcg_pwr_csb_load_gating_prod,
372 .blcg_xbar_load_gating_prod =
373 gm20b_blcg_xbar_load_gating_prod,
374 .blcg_pmu_load_gating_prod =
375 gm20b_blcg_pmu_load_gating_prod,
376 .pg_gr_load_gating_prod =
377 gr_gm20b_pg_gr_load_gating_prod,
378 },
379 .fifo = {
380 .init_fifo_setup_hw = gk20a_init_fifo_setup_hw,
381 .bind_channel = channel_gm20b_bind,
382 .unbind_channel = gk20a_fifo_channel_unbind,
383 .disable_channel = gk20a_fifo_disable_channel,
384 .enable_channel = gk20a_fifo_enable_channel,
385 .alloc_inst = gk20a_fifo_alloc_inst,
386 .free_inst = gk20a_fifo_free_inst,
387 .setup_ramfc = gk20a_fifo_setup_ramfc,
388 .channel_set_timeslice = gk20a_fifo_set_timeslice,
389 .default_timeslice_us = gk20a_fifo_default_timeslice_us,
390 .setup_userd = gk20a_fifo_setup_userd,
391 .userd_gp_get = gk20a_fifo_userd_gp_get,
392 .userd_gp_put = gk20a_fifo_userd_gp_put,
393 .userd_pb_get = gk20a_fifo_userd_pb_get,
394 .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val,
395 .preempt_channel = gk20a_fifo_preempt_channel,
396 .preempt_tsg = gk20a_fifo_preempt_tsg,
397 .enable_tsg = gk20a_enable_tsg,
398 .disable_tsg = gk20a_disable_tsg,
399 .tsg_verify_channel_status = gk20a_fifo_tsg_unbind_channel_verify_status,
400 .tsg_verify_status_ctx_reload = gm20b_fifo_tsg_verify_status_ctx_reload,
401 .update_runlist = gk20a_fifo_update_runlist,
402 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
403 .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info,
404 .wait_engine_idle = gk20a_fifo_wait_engine_idle,
405 .get_num_fifos = gm20b_fifo_get_num_fifos,
406 .get_pbdma_signature = gk20a_fifo_get_pbdma_signature,
407 .set_runlist_interleave = gk20a_fifo_set_runlist_interleave,
408 .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice,
409 .force_reset_ch = gk20a_fifo_force_reset_ch,
410 .engine_enum_from_type = gk20a_fifo_engine_enum_from_type,
411 .device_info_data_parse = gm20b_device_info_data_parse,
412 .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v,
413 .init_engine_info = gk20a_fifo_init_engine_info,
414 .runlist_entry_size = ram_rl_entry_size_v,
415 .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry,
416 .get_ch_runlist_entry = gk20a_get_ch_runlist_entry,
417 .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc,
418 .dump_pbdma_status = gk20a_dump_pbdma_status,
419 .dump_eng_status = gk20a_dump_eng_status,
420 .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc,
421 .intr_0_error_mask = gk20a_fifo_intr_0_error_mask,
422 .is_preempt_pending = gk20a_fifo_is_preempt_pending,
423 .init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs,
424 .reset_enable_hw = gk20a_init_fifo_reset_enable_hw,
425 .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg,
426 .handle_sched_error = gk20a_fifo_handle_sched_error,
427 .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0,
428 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
429 .tsg_bind_channel = gk20a_tsg_bind_channel,
430 .tsg_unbind_channel = gk20a_tsg_unbind_channel,
431#ifdef CONFIG_TEGRA_GK20A_NVHOST
432 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
433 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
434 .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd,
435 .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size,
436 .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd,
437 .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size,
438#endif
439 },
440 .gr_ctx = {
441 .get_netlist_name = gr_gm20b_get_netlist_name,
442 .is_fw_defined = gr_gm20b_is_firmware_defined,
443 },
444 .mm = {
445 .support_sparse = gm20b_mm_support_sparse,
446 .gmmu_map = gk20a_locked_gmmu_map,
447 .gmmu_unmap = gk20a_locked_gmmu_unmap,
448 .vm_bind_channel = gk20a_vm_bind_channel,
449 .fb_flush = gk20a_mm_fb_flush,
450 .l2_invalidate = gk20a_mm_l2_invalidate,
451 .l2_flush = gk20a_mm_l2_flush,
452 .cbc_clean = gk20a_mm_cbc_clean,
453 .set_big_page_size = gm20b_mm_set_big_page_size,
454 .get_big_page_sizes = gm20b_mm_get_big_page_sizes,
455 .get_default_big_page_size = gm20b_mm_get_default_big_page_size,
456 .gpu_phys_addr = gm20b_gpu_phys_addr,
457 .get_iommu_bit = gk20a_mm_get_iommu_bit,
458 .get_mmu_levels = gk20a_mm_get_mmu_levels,
459 .init_pdb = gk20a_mm_init_pdb,
460 .init_mm_setup_hw = gk20a_init_mm_setup_hw,
461 .is_bar1_supported = gm20b_mm_is_bar1_supported,
462 .alloc_inst_block = gk20a_alloc_inst_block,
463 .init_inst_block = gk20a_init_inst_block,
464 .mmu_fault_pending = gk20a_fifo_mmu_fault_pending,
465 .get_kind_invalid = gm20b_get_kind_invalid,
466 .get_kind_pitch = gm20b_get_kind_pitch,
467 },
468 .therm = {
469 .init_therm_setup_hw = gm20b_init_therm_setup_hw,
470 .elcg_init_idle_filters = gk20a_elcg_init_idle_filters,
471 },
472 .pmu = {
473 .pmu_setup_elpg = gm20b_pmu_setup_elpg,
474 .pmu_get_queue_head = pwr_pmu_queue_head_r,
475 .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
476 .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
477 .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
478 .pmu_queue_head = gk20a_pmu_queue_head,
479 .pmu_queue_tail = gk20a_pmu_queue_tail,
480 .pmu_msgq_tail = gk20a_pmu_msgq_tail,
481 .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
482 .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
483 .pmu_mutex_release = gk20a_pmu_mutex_release,
484 .write_dmatrfbase = gm20b_write_dmatrfbase,
485 .pmu_elpg_statistics = gk20a_pmu_elpg_statistics,
486 .pmu_pg_init_param = NULL,
487 .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
488 .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
489 .pmu_is_lpwr_feature_supported = NULL,
490 .pmu_lpwr_enable_pg = NULL,
491 .pmu_lpwr_disable_pg = NULL,
492 .pmu_pg_param_post_init = NULL,
493 .dump_secure_fuses = pmu_dump_security_fuses_gm20b,
494 .reset_engine = gk20a_pmu_engine_reset,
495 .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
496 },
497 .clk = {
498 .init_clk_support = gm20b_init_clk_support,
499 .suspend_clk_support = gm20b_suspend_clk_support,
500#ifdef CONFIG_DEBUG_FS
501 .init_debugfs = gm20b_clk_init_debugfs,
502#endif
503 .get_voltage = gm20b_clk_get_voltage,
504 .get_gpcclk_clock_counter = gm20b_clk_get_gpcclk_clock_counter,
505 .pll_reg_write = gm20b_clk_pll_reg_write,
506 .get_pll_debug_data = gm20b_clk_get_pll_debug_data,
507 },
508 .regops = {
509 .get_global_whitelist_ranges =
510 gm20b_get_global_whitelist_ranges,
511 .get_global_whitelist_ranges_count =
512 gm20b_get_global_whitelist_ranges_count,
513 .get_context_whitelist_ranges =
514 gm20b_get_context_whitelist_ranges,
515 .get_context_whitelist_ranges_count =
516 gm20b_get_context_whitelist_ranges_count,
517 .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist,
518 .get_runcontrol_whitelist_count =
519 gm20b_get_runcontrol_whitelist_count,
520 .get_runcontrol_whitelist_ranges =
521 gm20b_get_runcontrol_whitelist_ranges,
522 .get_runcontrol_whitelist_ranges_count =
523 gm20b_get_runcontrol_whitelist_ranges_count,
524 .get_qctl_whitelist = gm20b_get_qctl_whitelist,
525 .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count,
526 .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges,
527 .get_qctl_whitelist_ranges_count =
528 gm20b_get_qctl_whitelist_ranges_count,
529 .apply_smpc_war = gm20b_apply_smpc_war,
530 },
531 .mc = {
532 .intr_enable = mc_gk20a_intr_enable,
533 .intr_unit_config = mc_gk20a_intr_unit_config,
534 .isr_stall = mc_gk20a_isr_stall,
535 .intr_stall = mc_gk20a_intr_stall,
536 .intr_stall_pause = mc_gk20a_intr_stall_pause,
537 .intr_stall_resume = mc_gk20a_intr_stall_resume,
538 .intr_nonstall = mc_gk20a_intr_nonstall,
539 .intr_nonstall_pause = mc_gk20a_intr_nonstall_pause,
540 .intr_nonstall_resume = mc_gk20a_intr_nonstall_resume,
541 .enable = gk20a_mc_enable,
542 .disable = gk20a_mc_disable,
543 .reset = gk20a_mc_reset,
544 .boot_0 = gk20a_mc_boot_0,
545 .is_intr1_pending = mc_gk20a_is_intr1_pending,
546 },
547 .debug = {
548 .show_dump = gk20a_debug_show_dump,
549 },
550 .dbg_session_ops = {
551 .exec_reg_ops = exec_regops_gk20a,
552 .dbg_set_powergate = dbg_set_powergate,
553 .check_and_set_global_reservation =
554 nvgpu_check_and_set_global_reservation,
555 .check_and_set_context_reservation =
556 nvgpu_check_and_set_context_reservation,
557 .release_profiler_reservation =
558 nvgpu_release_profiler_reservation,
559 .perfbuffer_enable = gk20a_perfbuf_enable_locked,
560 .perfbuffer_disable = gk20a_perfbuf_disable_locked,
561 },
562 .bus = {
563 .init_hw = gk20a_bus_init_hw,
564 .isr = gk20a_bus_isr,
565 .read_ptimer = gk20a_read_ptimer,
566 .get_timestamps_zipper = nvgpu_get_timestamps_zipper,
567 .bar1_bind = gm20b_bus_bar1_bind,
568 },
569#if defined(CONFIG_GK20A_CYCLE_STATS)
570 .css = {
571 .enable_snapshot = css_hw_enable_snapshot,
572 .disable_snapshot = css_hw_disable_snapshot,
573 .check_data_available = css_hw_check_data_available,
574 .set_handled_snapshots = css_hw_set_handled_snapshots,
575 .allocate_perfmon_ids = css_gr_allocate_perfmon_ids,
576 .release_perfmon_ids = css_gr_release_perfmon_ids,
577 },
578#endif
579 .falcon = {
580 .falcon_hal_sw_init = gk20a_falcon_hal_sw_init,
581 },
582 .priv_ring = {
583 .isr = gk20a_priv_ring_isr,
584 },
585 .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics,
586 .get_litter_value = gm20b_get_litter_value,
587};
588
589int gm20b_init_hal(struct gk20a *g)
590{
591 struct gpu_ops *gops = &g->ops;
592 u32 val;
593
594 gops->ltc = gm20b_ops.ltc;
595 gops->ce2 = gm20b_ops.ce2;
596 gops->gr = gm20b_ops.gr;
597 gops->fb = gm20b_ops.fb;
598 gops->clock_gating = gm20b_ops.clock_gating;
599 gops->fifo = gm20b_ops.fifo;
600 gops->gr_ctx = gm20b_ops.gr_ctx;
601 gops->mm = gm20b_ops.mm;
602 gops->therm = gm20b_ops.therm;
603 gops->pmu = gm20b_ops.pmu;
604 /*
605 * clk must be assigned member by member
606 * since some clk ops are assigned during probe prior to HAL init
607 */
608 gops->clk.init_clk_support = gm20b_ops.clk.init_clk_support;
609 gops->clk.suspend_clk_support = gm20b_ops.clk.suspend_clk_support;
610 gops->clk.get_voltage = gm20b_ops.clk.get_voltage;
611 gops->clk.get_gpcclk_clock_counter =
612 gm20b_ops.clk.get_gpcclk_clock_counter;
613 gops->clk.pll_reg_write = gm20b_ops.clk.pll_reg_write;
614 gops->clk.get_pll_debug_data = gm20b_ops.clk.get_pll_debug_data;
615
616 gops->regops = gm20b_ops.regops;
617 gops->mc = gm20b_ops.mc;
618 gops->dbg_session_ops = gm20b_ops.dbg_session_ops;
619 gops->debug = gm20b_ops.debug;
620 gops->bus = gm20b_ops.bus;
621#if defined(CONFIG_GK20A_CYCLE_STATS)
622 gops->css = gm20b_ops.css;
623#endif
624 gops->falcon = gm20b_ops.falcon;
625
626 gops->priv_ring = gm20b_ops.priv_ring;
627
628 /* Lone functions */
629 gops->chip_init_gpu_characteristics =
630 gm20b_ops.chip_init_gpu_characteristics;
631 gops->get_litter_value = gm20b_ops.get_litter_value;
632
633 __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true);
634 __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
635 __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
636
637#ifdef CONFIG_TEGRA_ACR
638 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
639 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
640 } else {
641 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
642 if (!val) {
643 gk20a_dbg_info("priv security is disabled in HW");
644 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
645 } else {
646 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
647 }
648 }
649#else
650 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
651 gk20a_dbg_info("running ASIM with PRIV security disabled");
652 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
653 } else {
654 val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
655 if (!val) {
656 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
657 } else {
658 gk20a_dbg_info("priv security is not supported but enabled");
659 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
660 return -EPERM;
661 }
662 }
663#endif
664
665 /* priv security dependent ops */
666 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
667 /* Add in ops from gm20b acr */
668 gops->pmu.is_pmu_supported = gm20b_is_pmu_supported;
669 gops->pmu.prepare_ucode = prepare_ucode_blob;
670 gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn;
671 gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap;
672 gops->pmu.is_priv_load = gm20b_is_priv_load;
673 gops->pmu.get_wpr = gm20b_wpr_info;
674 gops->pmu.alloc_blob_space = gm20b_alloc_blob_space;
675 gops->pmu.pmu_populate_loader_cfg =
676 gm20b_pmu_populate_loader_cfg;
677 gops->pmu.flcn_populate_bl_dmem_desc =
678 gm20b_flcn_populate_bl_dmem_desc;
679 gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt;
680 gops->pmu.falcon_clear_halt_interrupt_status =
681 clear_halt_interrupt_status;
682 gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1;
683
684 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
685 gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode;
686
687 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
688 } else {
689 /* Inherit from gk20a */
690 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported;
691 gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob;
692 gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1;
693 gops->pmu.pmu_nsbootstrap = pmu_bootstrap;
694
695 gops->pmu.load_lsfalcon_ucode = NULL;
696 gops->pmu.init_wpr_region = NULL;
697
698 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
699 }
700
701 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
702 g->pmu_lsf_pmu_wpr_init_done = 0;
703 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
704
705 g->name = "gm20b";
706
707 return 0;
708}
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