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path: root/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hal_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c142
1 files changed, 74 insertions, 68 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index d22caab8..4d2e56d5 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -46,72 +46,6 @@
46 46
47#define PRIV_SECURITY_DISABLE 0x01 47#define PRIV_SECURITY_DISABLE 0x01
48 48
49static const struct gpu_ops gm20b_ops = {
50 .ltc = {
51 .determine_L2_size_bytes = gm20b_determine_L2_size_bytes,
52 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
53 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
54 .init_cbc = gm20b_ltc_init_cbc,
55 .init_fs_state = gm20b_ltc_init_fs_state,
56 .init_comptags = gm20b_ltc_init_comptags,
57 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
58 .isr = gm20b_ltc_isr,
59 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
60 .flush = gm20b_flush_ltc,
61#ifdef CONFIG_DEBUG_FS
62 .sync_debugfs = gm20b_ltc_sync_debugfs,
63#endif
64 },
65 .clock_gating = {
66 .slcg_bus_load_gating_prod =
67 gm20b_slcg_bus_load_gating_prod,
68 .slcg_ce2_load_gating_prod =
69 gm20b_slcg_ce2_load_gating_prod,
70 .slcg_chiplet_load_gating_prod =
71 gm20b_slcg_chiplet_load_gating_prod,
72 .slcg_ctxsw_firmware_load_gating_prod =
73 gm20b_slcg_ctxsw_firmware_load_gating_prod,
74 .slcg_fb_load_gating_prod =
75 gm20b_slcg_fb_load_gating_prod,
76 .slcg_fifo_load_gating_prod =
77 gm20b_slcg_fifo_load_gating_prod,
78 .slcg_gr_load_gating_prod =
79 gr_gm20b_slcg_gr_load_gating_prod,
80 .slcg_ltc_load_gating_prod =
81 ltc_gm20b_slcg_ltc_load_gating_prod,
82 .slcg_perf_load_gating_prod =
83 gm20b_slcg_perf_load_gating_prod,
84 .slcg_priring_load_gating_prod =
85 gm20b_slcg_priring_load_gating_prod,
86 .slcg_pmu_load_gating_prod =
87 gm20b_slcg_pmu_load_gating_prod,
88 .slcg_therm_load_gating_prod =
89 gm20b_slcg_therm_load_gating_prod,
90 .slcg_xbar_load_gating_prod =
91 gm20b_slcg_xbar_load_gating_prod,
92 .blcg_bus_load_gating_prod =
93 gm20b_blcg_bus_load_gating_prod,
94 .blcg_ctxsw_firmware_load_gating_prod =
95 gm20b_blcg_ctxsw_firmware_load_gating_prod,
96 .blcg_fb_load_gating_prod =
97 gm20b_blcg_fb_load_gating_prod,
98 .blcg_fifo_load_gating_prod =
99 gm20b_blcg_fifo_load_gating_prod,
100 .blcg_gr_load_gating_prod =
101 gm20b_blcg_gr_load_gating_prod,
102 .blcg_ltc_load_gating_prod =
103 gm20b_blcg_ltc_load_gating_prod,
104 .blcg_pwr_csb_load_gating_prod =
105 gm20b_blcg_pwr_csb_load_gating_prod,
106 .blcg_xbar_load_gating_prod =
107 gm20b_blcg_xbar_load_gating_prod,
108 .blcg_pmu_load_gating_prod =
109 gm20b_blcg_pmu_load_gating_prod,
110 .pg_gr_load_gating_prod =
111 gr_gm20b_pg_gr_load_gating_prod,
112 },
113};
114
115static int gm20b_get_litter_value(struct gk20a *g, int value) 49static int gm20b_get_litter_value(struct gk20a *g, int value)
116{ 50{
117 int ret = EINVAL; 51 int ret = EINVAL;
@@ -201,6 +135,74 @@ static int gm20b_get_litter_value(struct gk20a *g, int value)
201 return ret; 135 return ret;
202} 136}
203 137
138static const struct gpu_ops gm20b_ops = {
139 .ltc = {
140 .determine_L2_size_bytes = gm20b_determine_L2_size_bytes,
141 .set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry,
142 .set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry,
143 .init_cbc = gm20b_ltc_init_cbc,
144 .init_fs_state = gm20b_ltc_init_fs_state,
145 .init_comptags = gm20b_ltc_init_comptags,
146 .cbc_ctrl = gm20b_ltc_cbc_ctrl,
147 .isr = gm20b_ltc_isr,
148 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
149 .flush = gm20b_flush_ltc,
150#ifdef CONFIG_DEBUG_FS
151 .sync_debugfs = gm20b_ltc_sync_debugfs,
152#endif
153 },
154 .clock_gating = {
155 .slcg_bus_load_gating_prod =
156 gm20b_slcg_bus_load_gating_prod,
157 .slcg_ce2_load_gating_prod =
158 gm20b_slcg_ce2_load_gating_prod,
159 .slcg_chiplet_load_gating_prod =
160 gm20b_slcg_chiplet_load_gating_prod,
161 .slcg_ctxsw_firmware_load_gating_prod =
162 gm20b_slcg_ctxsw_firmware_load_gating_prod,
163 .slcg_fb_load_gating_prod =
164 gm20b_slcg_fb_load_gating_prod,
165 .slcg_fifo_load_gating_prod =
166 gm20b_slcg_fifo_load_gating_prod,
167 .slcg_gr_load_gating_prod =
168 gr_gm20b_slcg_gr_load_gating_prod,
169 .slcg_ltc_load_gating_prod =
170 ltc_gm20b_slcg_ltc_load_gating_prod,
171 .slcg_perf_load_gating_prod =
172 gm20b_slcg_perf_load_gating_prod,
173 .slcg_priring_load_gating_prod =
174 gm20b_slcg_priring_load_gating_prod,
175 .slcg_pmu_load_gating_prod =
176 gm20b_slcg_pmu_load_gating_prod,
177 .slcg_therm_load_gating_prod =
178 gm20b_slcg_therm_load_gating_prod,
179 .slcg_xbar_load_gating_prod =
180 gm20b_slcg_xbar_load_gating_prod,
181 .blcg_bus_load_gating_prod =
182 gm20b_blcg_bus_load_gating_prod,
183 .blcg_ctxsw_firmware_load_gating_prod =
184 gm20b_blcg_ctxsw_firmware_load_gating_prod,
185 .blcg_fb_load_gating_prod =
186 gm20b_blcg_fb_load_gating_prod,
187 .blcg_fifo_load_gating_prod =
188 gm20b_blcg_fifo_load_gating_prod,
189 .blcg_gr_load_gating_prod =
190 gm20b_blcg_gr_load_gating_prod,
191 .blcg_ltc_load_gating_prod =
192 gm20b_blcg_ltc_load_gating_prod,
193 .blcg_pwr_csb_load_gating_prod =
194 gm20b_blcg_pwr_csb_load_gating_prod,
195 .blcg_xbar_load_gating_prod =
196 gm20b_blcg_xbar_load_gating_prod,
197 .blcg_pmu_load_gating_prod =
198 gm20b_blcg_pmu_load_gating_prod,
199 .pg_gr_load_gating_prod =
200 gr_gm20b_pg_gr_load_gating_prod,
201 },
202 .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics,
203 .get_litter_value = gm20b_get_litter_value,
204};
205
204int gm20b_init_hal(struct gk20a *g) 206int gm20b_init_hal(struct gk20a *g)
205{ 207{
206 struct gpu_ops *gops = &g->ops; 208 struct gpu_ops *gops = &g->ops;
@@ -209,6 +211,12 @@ int gm20b_init_hal(struct gk20a *g)
209 211
210 gops->ltc = gm20b_ops.ltc; 212 gops->ltc = gm20b_ops.ltc;
211 gops->clock_gating = gm20b_ops.clock_gating; 213 gops->clock_gating = gm20b_ops.clock_gating;
214
215 /* Lone functions */
216 gops->chip_init_gpu_characteristics =
217 gm20b_ops.chip_init_gpu_characteristics;
218 gops->get_litter_value = gm20b_ops.get_litter_value;
219
212 gops->securegpccs = false; 220 gops->securegpccs = false;
213 gops->pmupstate = false; 221 gops->pmupstate = false;
214#ifdef CONFIG_TEGRA_ACR 222#ifdef CONFIG_TEGRA_ACR
@@ -260,8 +268,6 @@ int gm20b_init_hal(struct gk20a *g)
260 gk20a_init_css_ops(gops); 268 gk20a_init_css_ops(gops);
261#endif 269#endif
262 g->name = "gm20b"; 270 g->name = "gm20b";
263 gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
264 gops->get_litter_value = gm20b_get_litter_value;
265 271
266 c->twod_class = FERMI_TWOD_A; 272 c->twod_class = FERMI_TWOD_A;
267 c->threed_class = MAXWELL_B; 273 c->threed_class = MAXWELL_B;
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-02 20:29:06 -0400