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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.h')
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index 084b6157..81916c05 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GM20B GPC MMU 2 * GM20B GPC MMU
3 * 3 *
4 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -125,5 +125,7 @@ int gr_gm20b_get_preemption_mode_flags(struct gk20a *g,
125void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, 125void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
126 u32 global_esr); 126 u32 global_esr);
127u32 gr_gm20b_get_pmm_per_chiplet_offset(void); 127u32 gr_gm20b_get_pmm_per_chiplet_offset(void);
128int gm20b_gr_set_mmu_debug_mode(struct gk20a *g,
129 struct channel_gk20a *ch, bool enable);
128void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); 130void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable);
129#endif /* NVGPU_GM20B_GR_GM20B_H */ 131#endif /* NVGPU_GM20B_GR_GM20B_H */