diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 01537042..fc98b5ca 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -511,23 +511,18 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | |||
511 | 511 | ||
512 | static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 512 | static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
513 | { | 513 | { |
514 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) | ||
515 | tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); | ||
516 | tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0); | ||
517 | #else | ||
518 | tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0); | 514 | tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0); |
519 | tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0); | 515 | tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0); |
520 | #endif | ||
521 | 516 | ||
522 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) { | 517 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) { |
523 | tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); | 518 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); |
524 | tegra_fuse_writel(0x1, FUSE_OPT_GPU_TPC1_DISABLE_0); | 519 | tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC1_DISABLE_0); |
525 | } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) { | 520 | } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) { |
526 | tegra_fuse_writel(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); | 521 | tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); |
527 | tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0); | 522 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0); |
528 | } else { | 523 | } else { |
529 | tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); | 524 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); |
530 | tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0); | 525 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0); |
531 | } | 526 | } |
532 | } | 527 | } |
533 | 528 | ||