diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 368c9321..c67f7870 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -550,6 +550,23 @@ void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, | |||
550 | ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); | 550 | ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); |
551 | } | 551 | } |
552 | 552 | ||
553 | u32 gr_gm20b_get_gpc_mask(struct gk20a *g) | ||
554 | { | ||
555 | u32 val; | ||
556 | struct gr_gk20a *gr = &g->gr; | ||
557 | |||
558 | /* | ||
559 | * For register NV_FUSE_STATUS_OPT_GPC a set bit with index i indicates | ||
560 | * corresponding GPC is floorswept | ||
561 | * But for s/w mask a set bit means GPC is enabled and it is disabled | ||
562 | * otherwise | ||
563 | * Hence toggle the bits of register value to get s/w mask | ||
564 | */ | ||
565 | val = g->ops.fuse.fuse_status_opt_gpc(g); | ||
566 | |||
567 | return (~val) & (BIT32(gr->max_gpc_count) - 1U); | ||
568 | } | ||
569 | |||
553 | u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 570 | u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
554 | { | 571 | { |
555 | u32 val; | 572 | u32 val; |