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path: root/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c12
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 0375d71f..9cf644fd 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1247,7 +1247,7 @@ static int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
1247 GPU_LIT_TPC_IN_GPC_STRIDE); 1247 GPU_LIT_TPC_IN_GPC_STRIDE);
1248 u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; 1248 u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc;
1249 1249
1250 mutex_lock(&g->dbg_sessions_lock); 1250 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
1251 1251
1252 sm_id = gr_gpc0_tpc0_sm_cfg_sm_id_v(gk20a_readl(g, 1252 sm_id = gr_gpc0_tpc0_sm_cfg_sm_id_v(gk20a_readl(g,
1253 gr_gpc0_tpc0_sm_cfg_r() + offset)); 1253 gr_gpc0_tpc0_sm_cfg_r() + offset));
@@ -1263,7 +1263,7 @@ static int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
1263 gr->sm_error_states[sm_id].hww_warp_esr_report_mask = gk20a_readl(g, 1263 gr->sm_error_states[sm_id].hww_warp_esr_report_mask = gk20a_readl(g,
1264 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r() + offset); 1264 gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r() + offset);
1265 1265
1266 mutex_unlock(&g->dbg_sessions_lock); 1266 nvgpu_mutex_release(&g->dbg_sessions_lock);
1267 1267
1268 return 0; 1268 return 0;
1269} 1269}
@@ -1280,7 +1280,7 @@ static int gm20b_gr_update_sm_error_state(struct gk20a *g,
1280 GPU_LIT_TPC_IN_GPC_STRIDE); 1280 GPU_LIT_TPC_IN_GPC_STRIDE);
1281 int err = 0; 1281 int err = 0;
1282 1282
1283 mutex_lock(&g->dbg_sessions_lock); 1283 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
1284 1284
1285 gr->sm_error_states[sm_id].hww_global_esr = 1285 gr->sm_error_states[sm_id].hww_global_esr =
1286 sm_error_state->hww_global_esr; 1286 sm_error_state->hww_global_esr;
@@ -1336,7 +1336,7 @@ enable_ctxsw:
1336 err = gr_gk20a_enable_ctxsw(g); 1336 err = gr_gk20a_enable_ctxsw(g);
1337 1337
1338fail: 1338fail:
1339 mutex_unlock(&g->dbg_sessions_lock); 1339 nvgpu_mutex_release(&g->dbg_sessions_lock);
1340 return err; 1340 return err;
1341} 1341}
1342 1342
@@ -1351,7 +1351,7 @@ static int gm20b_gr_clear_sm_error_state(struct gk20a *g,
1351 GPU_LIT_TPC_IN_GPC_STRIDE); 1351 GPU_LIT_TPC_IN_GPC_STRIDE);
1352 int err = 0; 1352 int err = 0;
1353 1353
1354 mutex_lock(&g->dbg_sessions_lock); 1354 nvgpu_mutex_acquire(&g->dbg_sessions_lock);
1355 1355
1356 memset(&gr->sm_error_states[sm_id], 0, sizeof(*gr->sm_error_states)); 1356 memset(&gr->sm_error_states[sm_id], 0, sizeof(*gr->sm_error_states));
1357 1357
@@ -1377,7 +1377,7 @@ static int gm20b_gr_clear_sm_error_state(struct gk20a *g,
1377 err = gr_gk20a_enable_ctxsw(g); 1377 err = gr_gk20a_enable_ctxsw(g);
1378 1378
1379fail: 1379fail:
1380 mutex_unlock(&g->dbg_sessions_lock); 1380 nvgpu_mutex_release(&g->dbg_sessions_lock);
1381 return err; 1381 return err;
1382} 1382}
1383 1383