diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 19 |
1 files changed, 9 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index c6e451e1..b7fb1ac5 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -13,14 +13,13 @@ | |||
13 | * more details. | 13 | * more details. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <soc/tegra/fuse.h> | ||
17 | |||
18 | #include <dt-bindings/soc/gm20b-fuse.h> | 16 | #include <dt-bindings/soc/gm20b-fuse.h> |
19 | 17 | ||
20 | #include <nvgpu/kmem.h> | 18 | #include <nvgpu/kmem.h> |
21 | #include <nvgpu/log.h> | 19 | #include <nvgpu/log.h> |
22 | #include <nvgpu/enabled.h> | 20 | #include <nvgpu/enabled.h> |
23 | #include <nvgpu/debug.h> | 21 | #include <nvgpu/debug.h> |
22 | #include <nvgpu/fuse.h> | ||
24 | 23 | ||
25 | #include "gk20a/gk20a.h" | 24 | #include "gk20a/gk20a.h" |
26 | #include "gk20a/gr_gk20a.h" | 25 | #include "gk20a/gr_gk20a.h" |
@@ -548,18 +547,18 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | |||
548 | 547 | ||
549 | static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 548 | static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
550 | { | 549 | { |
551 | tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0); | 550 | nvgpu_tegra_fuse_write_bypass(0x1); |
552 | tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0); | 551 | nvgpu_tegra_fuse_write_access_sw(0x0); |
553 | 552 | ||
554 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) { | 553 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) { |
555 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); | 554 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); |
556 | tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC1_DISABLE_0); | 555 | nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x1); |
557 | } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) { | 556 | } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) { |
558 | tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0); | 557 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x1); |
559 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0); | 558 | nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0); |
560 | } else { | 559 | } else { |
561 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0); | 560 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(0x0); |
562 | tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0); | 561 | nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(0x0); |
563 | } | 562 | } |
564 | } | 563 | } |
565 | 564 | ||