diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index b49f2301..eeb70d76 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include "hw_fuse_gm20b.h" | 31 | #include "hw_fuse_gm20b.h" |
32 | #include "pmu_gm20b.h" | 32 | #include "pmu_gm20b.h" |
33 | #include "acr_gm20b.h" | 33 | #include "acr_gm20b.h" |
34 | #include "hw_proj_gm20b.h" | ||
34 | 35 | ||
35 | static void gr_gm20b_init_gpc_mmu(struct gk20a *g) | 36 | static void gr_gm20b_init_gpc_mmu(struct gk20a *g) |
36 | { | 37 | { |
@@ -1190,6 +1191,34 @@ static void gr_gm20b_get_access_map(struct gk20a *g, | |||
1190 | *num_entries = ARRAY_SIZE(wl_addr_gm20b); | 1191 | *num_entries = ARRAY_SIZE(wl_addr_gm20b); |
1191 | } | 1192 | } |
1192 | 1193 | ||
1194 | static int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) | ||
1195 | { | ||
1196 | int sm_id; | ||
1197 | struct gr_gk20a *gr = &g->gr; | ||
1198 | u32 offset = proj_gpc_stride_v() * gpc + | ||
1199 | proj_tpc_in_gpc_stride_v() * tpc; | ||
1200 | |||
1201 | mutex_lock(&g->dbg_sessions_lock); | ||
1202 | |||
1203 | sm_id = gr_gpc0_tpc0_sm_cfg_sm_id_v(gk20a_readl(g, | ||
1204 | gr_gpc0_tpc0_sm_cfg_r() + offset)); | ||
1205 | |||
1206 | gr->sm_error_states[sm_id].hww_global_esr = gk20a_readl(g, | ||
1207 | gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); | ||
1208 | gr->sm_error_states[sm_id].hww_warp_esr = gk20a_readl(g, | ||
1209 | gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset); | ||
1210 | gr->sm_error_states[sm_id].hww_warp_esr_pc = gk20a_readl(g, | ||
1211 | gr_gpc0_tpc0_sm_hww_warp_esr_pc_r() + offset); | ||
1212 | gr->sm_error_states[sm_id].hww_global_esr_report_mask = gk20a_readl(g, | ||
1213 | gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() + offset); | ||
1214 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask = gk20a_readl(g, | ||
1215 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() + offset); | ||
1216 | |||
1217 | mutex_unlock(&g->dbg_sessions_lock); | ||
1218 | |||
1219 | return 0; | ||
1220 | } | ||
1221 | |||
1193 | void gm20b_init_gr(struct gpu_ops *gops) | 1222 | void gm20b_init_gr(struct gpu_ops *gops) |
1194 | { | 1223 | { |
1195 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; | 1224 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; |
@@ -1256,4 +1285,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1256 | gops->gr.get_lrf_tex_ltc_dram_override = NULL; | 1285 | gops->gr.get_lrf_tex_ltc_dram_override = NULL; |
1257 | gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode; | 1286 | gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode; |
1258 | gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode; | 1287 | gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode; |
1288 | gops->gr.record_sm_error_state = gm20b_gr_record_sm_error_state; | ||
1259 | } | 1289 | } |