summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/fifo_gm20b.h')
-rw-r--r--drivers/gpu/nvgpu/gm20b/fifo_gm20b.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
index 8d487358..f9e1f95d 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * GM20B Fifo 2 * GM20B Fifo
3 * 3 *
4 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
25#ifndef _NVHOST_GM20B_FIFO 25#ifndef _NVHOST_GM20B_FIFO
26#define _NVHOST_GM20B_FIFO 26#define _NVHOST_GM20B_FIFO
27struct gk20a; 27struct gk20a;
28struct mmu_fault_info;
28 29
29void channel_gm20b_bind(struct channel_gk20a *c); 30void channel_gm20b_bind(struct channel_gk20a *c);
30void gm20b_fifo_trigger_mmu_fault(struct gk20a *g, 31void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
@@ -35,5 +36,6 @@ void gm20b_device_info_data_parse(struct gk20a *g,
35 u32 *pri_base, u32 *fault_id); 36 u32 *pri_base, u32 *fault_id);
36void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f); 37void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
37void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch); 38void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch);
39void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault);
38 40
39#endif 41#endif