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path: root/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/fifo_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/fifo_gm20b.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index b9763224..188d1781 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -20,25 +20,25 @@
20#include "hw_ram_gm20b.h" 20#include "hw_ram_gm20b.h"
21#include "hw_fifo_gm20b.h" 21#include "hw_fifo_gm20b.h"
22 22
23static void channel_gm20b_bind(struct channel_gk20a *ch_gk20a) 23static void channel_gm20b_bind(struct channel_gk20a *c)
24{ 24{
25 struct gk20a *g = ch_gk20a->g; 25 struct gk20a *g = c->g;
26 26
27 u32 inst_ptr = gk20a_mem_phys(&ch_gk20a->inst_block) 27 u32 inst_ptr = gk20a_mm_inst_block_addr(g, &c->inst_block)
28 >> ram_in_base_shift_v(); 28 >> ram_in_base_shift_v();
29 29
30 gk20a_dbg_info("bind channel %d inst ptr 0x%08x", 30 gk20a_dbg_info("bind channel %d inst ptr 0x%08x",
31 ch_gk20a->hw_chid, inst_ptr); 31 c->hw_chid, inst_ptr);
32 32
33 ch_gk20a->bound = true; 33 c->bound = true;
34 34
35 gk20a_writel(g, ccsr_channel_inst_r(ch_gk20a->hw_chid), 35 gk20a_writel(g, ccsr_channel_inst_r(c->hw_chid),
36 ccsr_channel_inst_ptr_f(inst_ptr) | 36 ccsr_channel_inst_ptr_f(inst_ptr) |
37 ccsr_channel_inst_target_vid_mem_f() | 37 ccsr_channel_inst_target_vid_mem_f() |
38 ccsr_channel_inst_bind_true_f()); 38 ccsr_channel_inst_bind_true_f());
39 39
40 gk20a_writel(g, ccsr_channel_r(ch_gk20a->hw_chid), 40 gk20a_writel(g, ccsr_channel_r(c->hw_chid),
41 (gk20a_readl(g, ccsr_channel_r(ch_gk20a->hw_chid)) & 41 (gk20a_readl(g, ccsr_channel_r(c->hw_chid)) &
42 ~ccsr_channel_enable_set_f(~0)) | 42 ~ccsr_channel_enable_set_f(~0)) |
43 ccsr_channel_enable_set_true_f()); 43 ccsr_channel_enable_set_true_f());
44} 44}