diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/fb_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fb_gm20b.c | 195 |
1 files changed, 195 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fb_gm20b.c b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c new file mode 100644 index 00000000..1f8cc326 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/fb_gm20b.c | |||
@@ -0,0 +1,195 @@ | |||
1 | /* | ||
2 | * GM20B GPC MMU | ||
3 | * | ||
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | #include "gk20a/fb_gk20a.h" | ||
27 | #include "gm20b/fb_gm20b.h" | ||
28 | |||
29 | #include <nvgpu/hw/gm20b/hw_fb_gm20b.h> | ||
30 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> | ||
31 | #include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h> | ||
32 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> | ||
33 | |||
34 | #define VPR_INFO_FETCH_WAIT (5) | ||
35 | #define WPR_INFO_ADDR_ALIGNMENT 0x0000000c | ||
36 | |||
37 | void fb_gm20b_init_fs_state(struct gk20a *g) | ||
38 | { | ||
39 | gk20a_dbg_info("initialize gm20b fb"); | ||
40 | |||
41 | gk20a_writel(g, fb_fbhub_num_active_ltcs_r(), | ||
42 | g->ltc_count); | ||
43 | } | ||
44 | |||
45 | void gm20b_fb_set_mmu_page_size(struct gk20a *g) | ||
46 | { | ||
47 | /* set large page size in fb */ | ||
48 | u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r()); | ||
49 | fb_mmu_ctrl |= fb_mmu_ctrl_use_pdb_big_page_size_true_f(); | ||
50 | gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl); | ||
51 | } | ||
52 | |||
53 | bool gm20b_fb_set_use_full_comp_tag_line(struct gk20a *g) | ||
54 | { | ||
55 | /* set large page size in fb */ | ||
56 | u32 fb_mmu_ctrl = gk20a_readl(g, fb_mmu_ctrl_r()); | ||
57 | fb_mmu_ctrl |= fb_mmu_ctrl_use_full_comp_tag_line_true_f(); | ||
58 | gk20a_writel(g, fb_mmu_ctrl_r(), fb_mmu_ctrl); | ||
59 | |||
60 | return true; | ||
61 | } | ||
62 | |||
63 | unsigned int gm20b_fb_compression_page_size(struct gk20a *g) | ||
64 | { | ||
65 | return SZ_128K; | ||
66 | } | ||
67 | |||
68 | unsigned int gm20b_fb_compressible_page_size(struct gk20a *g) | ||
69 | { | ||
70 | return SZ_64K; | ||
71 | } | ||
72 | |||
73 | void gm20b_fb_dump_vpr_wpr_info(struct gk20a *g) | ||
74 | { | ||
75 | u32 val; | ||
76 | |||
77 | /* print vpr and wpr info */ | ||
78 | val = gk20a_readl(g, fb_mmu_vpr_info_r()); | ||
79 | val &= ~0x3; | ||
80 | val |= fb_mmu_vpr_info_index_addr_lo_v(); | ||
81 | gk20a_writel(g, fb_mmu_vpr_info_r(), val); | ||
82 | nvgpu_err(g, "VPR: %08x %08x %08x %08x", | ||
83 | gk20a_readl(g, fb_mmu_vpr_info_r()), | ||
84 | gk20a_readl(g, fb_mmu_vpr_info_r()), | ||
85 | gk20a_readl(g, fb_mmu_vpr_info_r()), | ||
86 | gk20a_readl(g, fb_mmu_vpr_info_r())); | ||
87 | |||
88 | val = gk20a_readl(g, fb_mmu_wpr_info_r()); | ||
89 | val &= ~0xf; | ||
90 | val |= (fb_mmu_wpr_info_index_allow_read_v()); | ||
91 | gk20a_writel(g, fb_mmu_wpr_info_r(), val); | ||
92 | nvgpu_err(g, "WPR: %08x %08x %08x %08x %08x %08x", | ||
93 | gk20a_readl(g, fb_mmu_wpr_info_r()), | ||
94 | gk20a_readl(g, fb_mmu_wpr_info_r()), | ||
95 | gk20a_readl(g, fb_mmu_wpr_info_r()), | ||
96 | gk20a_readl(g, fb_mmu_wpr_info_r()), | ||
97 | gk20a_readl(g, fb_mmu_wpr_info_r()), | ||
98 | gk20a_readl(g, fb_mmu_wpr_info_r())); | ||
99 | |||
100 | } | ||
101 | |||
102 | static int gm20b_fb_vpr_info_fetch_wait(struct gk20a *g, | ||
103 | unsigned int msec) | ||
104 | { | ||
105 | struct nvgpu_timeout timeout; | ||
106 | |||
107 | nvgpu_timeout_init(g, &timeout, msec, NVGPU_TIMER_CPU_TIMER); | ||
108 | |||
109 | do { | ||
110 | u32 val; | ||
111 | |||
112 | val = gk20a_readl(g, fb_mmu_vpr_info_r()); | ||
113 | if (fb_mmu_vpr_info_fetch_v(val) == | ||
114 | fb_mmu_vpr_info_fetch_false_v()) | ||
115 | return 0; | ||
116 | |||
117 | } while (!nvgpu_timeout_expired(&timeout)); | ||
118 | |||
119 | return -ETIMEDOUT; | ||
120 | } | ||
121 | |||
122 | int gm20b_fb_vpr_info_fetch(struct gk20a *g) | ||
123 | { | ||
124 | if (gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT)) { | ||
125 | return -ETIME; | ||
126 | } | ||
127 | |||
128 | gk20a_writel(g, fb_mmu_vpr_info_r(), | ||
129 | fb_mmu_vpr_info_fetch_true_v()); | ||
130 | |||
131 | return gm20b_fb_vpr_info_fetch_wait(g, VPR_INFO_FETCH_WAIT); | ||
132 | } | ||
133 | |||
134 | void gm20b_fb_read_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf) | ||
135 | { | ||
136 | u32 val = 0; | ||
137 | u64 wpr_start = 0; | ||
138 | u64 wpr_end = 0; | ||
139 | |||
140 | val = gk20a_readl(g, fb_mmu_wpr_info_r()); | ||
141 | val &= ~0xF; | ||
142 | val |= fb_mmu_wpr_info_index_wpr1_addr_lo_v(); | ||
143 | gk20a_writel(g, fb_mmu_wpr_info_r(), val); | ||
144 | |||
145 | val = gk20a_readl(g, fb_mmu_wpr_info_r()) >> 0x4; | ||
146 | wpr_start = hi32_lo32_to_u64( | ||
147 | (val >> (32 - WPR_INFO_ADDR_ALIGNMENT)), | ||
148 | (val << WPR_INFO_ADDR_ALIGNMENT)); | ||
149 | |||
150 | val = gk20a_readl(g, fb_mmu_wpr_info_r()); | ||
151 | val &= ~0xF; | ||
152 | val |= fb_mmu_wpr_info_index_wpr1_addr_hi_v(); | ||
153 | gk20a_writel(g, fb_mmu_wpr_info_r(), val); | ||
154 | |||
155 | val = gk20a_readl(g, fb_mmu_wpr_info_r()) >> 0x4; | ||
156 | wpr_end = hi32_lo32_to_u64( | ||
157 | (val >> (32 - WPR_INFO_ADDR_ALIGNMENT)), | ||
158 | (val << WPR_INFO_ADDR_ALIGNMENT)); | ||
159 | |||
160 | inf->wpr_base = wpr_start; | ||
161 | inf->nonwpr_base = 0; | ||
162 | inf->size = (wpr_end - wpr_start); | ||
163 | } | ||
164 | |||
165 | bool gm20b_fb_debug_mode_enabled(struct gk20a *g) | ||
166 | { | ||
167 | u32 debug_ctrl = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); | ||
168 | return gr_gpcs_pri_mmu_debug_ctrl_debug_v(debug_ctrl) == | ||
169 | gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_v(); | ||
170 | } | ||
171 | |||
172 | void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) | ||
173 | { | ||
174 | u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl; | ||
175 | |||
176 | if (enable) { | ||
177 | fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); | ||
178 | gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(); | ||
179 | g->mmu_debug_ctrl = true; | ||
180 | } else { | ||
181 | fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); | ||
182 | gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(); | ||
183 | g->mmu_debug_ctrl = false; | ||
184 | } | ||
185 | |||
186 | reg_val = gk20a_readl(g, fb_mmu_debug_ctrl_r()); | ||
187 | reg_val = set_field(reg_val, | ||
188 | fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); | ||
189 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); | ||
190 | |||
191 | reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); | ||
192 | reg_val = set_field(reg_val, | ||
193 | gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); | ||
194 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); | ||
195 | } | ||