1 files changed, 8 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
index 1e06d651..07e0d04d 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.h
@@ -50,8 +50,6 @@ struct nvgpu_clk_pll_debug_data {
         u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset;
 };
 
-void gm20b_init_clk_ops(struct gpu_ops *gops);
-
 int gm20b_init_clk_setup_sw(struct gk20a *g);
 
 int gm20b_clk_prepare(struct clk_gk20a *clk);
@@ -67,6 +65,14 @@ struct pll_parms *gm20b_get_gpc_pll_parms(void);
 int gm20b_clk_init_debugfs(struct gk20a *g);
 #endif
 
+int gm20b_clk_pll_reg_write(struct gk20a *g, u32 reg, u32 val);
+int gm20b_init_clk_support(struct gk20a *g);
+int gm20b_suspend_clk_support(struct gk20a *g);
+int gm20b_clk_get_voltage(struct clk_gk20a *clk, u64 *val);
+int gm20b_clk_get_gpcclk_clock_counter(struct clk_gk20a *clk, u64 *val);
+int gm20b_clk_get_pll_debug_data(struct gk20a *g,
+                        struct nvgpu_clk_pll_debug_data *d);
+
 /* 1:1 match between post divider settings and divisor value */
 static inline u32 nvgpu_pl_to_div(u32 pl)
 {