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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/clk_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/clk_gm20b.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index 16f88d62..eb7703bd 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -43,7 +43,7 @@
43#define BOOT_GPU_UV 1000000 /* gpu rail boot voltage 1.0V */ 43#define BOOT_GPU_UV 1000000 /* gpu rail boot voltage 1.0V */
44#define ADC_SLOPE_UV 10000 /* default ADC detection slope 10mV */ 44#define ADC_SLOPE_UV 10000 /* default ADC detection slope 10mV */
45 45
46#define DVFS_SAFE_MARGIN 8 /* 8% */ 46#define DVFS_SAFE_MARGIN 10 /* 10% */
47static unsigned long dvfs_safe_max_freq; 47static unsigned long dvfs_safe_max_freq;
48 48
49static struct pll_parms gpc_pll_params = { 49static struct pll_parms gpc_pll_params = {
@@ -53,9 +53,9 @@ static struct pll_parms gpc_pll_params = {
53 1, 255, /* M */ 53 1, 255, /* M */
54 8, 255, /* N */ 54 8, 255, /* N */
55 1, 31, /* PL */ 55 1, 31, /* PL */
56 -58700, 86789, /* DFS_COEFF */ 56 -165230, 214007, /* DFS_COEFF */
57 0, 0, /* ADC char coeff - to be read from fuses */ 57 0, 0, /* ADC char coeff - to be read from fuses */
58 0, /* FIXME: vco control data */ 58 0x7 << 3, /* vco control in NA mode */
59}; 59};
60 60
61#ifdef CONFIG_DEBUG_FS 61#ifdef CONFIG_DEBUG_FS