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path: root/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/clk_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/clk_gm20b.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
index 71e21d58..1b01c74c 100644
--- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c
@@ -998,7 +998,7 @@ static int monitor_get(void *data, u64 *val)
998 u32 clk_slowdown, clk_slowdown_save; 998 u32 clk_slowdown, clk_slowdown_save;
999 int err; 999 int err;
1000 1000
1001 u32 ncycle = 100; /* count GPCCLK for ncycle of clkin */ 1001 u32 ncycle = 800; /* count GPCCLK for ncycle of clkin */
1002 u64 freq = clk->gpc_pll.clk_in; 1002 u64 freq = clk->gpc_pll.clk_in;
1003 u32 count1, count2; 1003 u32 count1, count2;
1004 1004
@@ -1024,7 +1024,7 @@ static int monitor_get(void *data, u64 *val)
1024 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(ncycle)); 1024 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(ncycle));
1025 /* start */ 1025 /* start */
1026 1026
1027 /* It should take less than 5us to finish 100 cycle of 38.4MHz. 1027 /* It should take less than 25us to finish 800 cycle of 38.4MHz.
1028 But longer than 100us delay is required here. */ 1028 But longer than 100us delay is required here. */
1029 gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0)); 1029 gk20a_readl(g, trim_gpc_clk_cntr_ncgpcclk_cfg_r(0));
1030 udelay(200); 1030 udelay(200);