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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/bus_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/bus_gm20b.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/bus_gm20b.c b/drivers/gpu/nvgpu/gm20b/bus_gm20b.c
index cdd70d5b..ca2a40bf 100644
--- a/drivers/gpu/nvgpu/gm20b/bus_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/bus_gm20b.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GM20B MMU 2 * GM20B MMU
3 * 3 *
4 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -40,7 +40,7 @@ int gm20b_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst)
40 u64 iova = nvgpu_inst_block_addr(g, bar1_inst); 40 u64 iova = nvgpu_inst_block_addr(g, bar1_inst);
41 u32 ptr_v = (u32)(iova >> bus_bar1_block_ptr_shift_v()); 41 u32 ptr_v = (u32)(iova >> bus_bar1_block_ptr_shift_v());
42 42
43 gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v); 43 nvgpu_log_info(g, "bar1 inst block ptr: 0x%08x", ptr_v);
44 44
45 gk20a_writel(g, bus_bar1_block_r(), 45 gk20a_writel(g, bus_bar1_block_r(),
46 nvgpu_aperture_mask(g, bar1_inst, 46 nvgpu_aperture_mask(g, bar1_inst,