diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/bus_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/bus_gm20b.c | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/bus_gm20b.c b/drivers/gpu/nvgpu/gm20b/bus_gm20b.c new file mode 100644 index 00000000..34c8d4b7 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/bus_gm20b.c | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * GM20B MMU | ||
3 | * | ||
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/timers.h> | ||
26 | #include <nvgpu/bus.h> | ||
27 | #include <nvgpu/mm.h> | ||
28 | |||
29 | #include "bus_gm20b.h" | ||
30 | #include "gk20a/gk20a.h" | ||
31 | #include "gk20a/bus_gk20a.h" | ||
32 | |||
33 | #include <nvgpu/hw/gm20b/hw_bus_gm20b.h> | ||
34 | |||
35 | int gm20b_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) | ||
36 | { | ||
37 | struct nvgpu_timeout timeout; | ||
38 | int err = 0; | ||
39 | u64 iova = nvgpu_inst_block_addr(g, bar1_inst); | ||
40 | u32 ptr_v = (u32)(iova >> bus_bar1_block_ptr_shift_v()); | ||
41 | |||
42 | gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v); | ||
43 | |||
44 | gk20a_writel(g, bus_bar1_block_r(), | ||
45 | nvgpu_aperture_mask(g, bar1_inst, | ||
46 | bus_bar1_block_target_sys_mem_ncoh_f(), | ||
47 | bus_bar1_block_target_vid_mem_f()) | | ||
48 | bus_bar1_block_mode_virtual_f() | | ||
49 | bus_bar1_block_ptr_f(ptr_v)); | ||
50 | nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); | ||
51 | do { | ||
52 | u32 val = gk20a_readl(g, bus_bind_status_r()); | ||
53 | u32 pending = bus_bind_status_bar1_pending_v(val); | ||
54 | u32 outstanding = bus_bind_status_bar1_outstanding_v(val); | ||
55 | if (!pending && !outstanding) | ||
56 | break; | ||
57 | |||
58 | nvgpu_udelay(5); | ||
59 | } while (!nvgpu_timeout_expired(&timeout)); | ||
60 | |||
61 | if (nvgpu_timeout_peek_expired(&timeout)) | ||
62 | err = -EINVAL; | ||
63 | |||
64 | return err; | ||
65 | } | ||