1 files changed, 14 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
index 84478611..6568d62f 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
@@ -24,8 +24,21 @@
 #define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
 #define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin"
 
-void gm20b_init_secure_pmu(struct gpu_ops *gops);
+bool gm20b_is_pmu_supported(struct gk20a *g);
 int prepare_ucode_blob(struct gk20a *g);
+int gm20b_bootstrap_hs_flcn(struct gk20a *g);
+bool gm20b_is_lazy_bootstrap(u32 falcon_id);
+bool gm20b_is_priv_load(u32 falcon_id);
+void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
+int gm20b_alloc_blob_space(struct gk20a *g, size_t size, struct nvgpu_mem *mem);
+int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
+        void *lsfm, u32 *p_bl_gen_desc_size);
+int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
+        void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
+int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms);
+int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
+int gm20b_init_pmu_setup_hw1(struct gk20a *g, void *desc, u32 bl_sz);
+
 int gm20b_pmu_setup_sw(struct gk20a *g);
 int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt);
 int gm20b_init_nspmu_setup_hw1(struct gk20a *g);