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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/acr_gm20b.h')
-rw-r--r--drivers/gpu/nvgpu/gm20b/acr_gm20b.h17
1 files changed, 14 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
index 329d53b8..cae6ab6a 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
@@ -37,21 +37,32 @@ bool gm20b_is_pmu_supported(struct gk20a *g);
37int prepare_ucode_blob(struct gk20a *g); 37int prepare_ucode_blob(struct gk20a *g);
38bool gm20b_is_lazy_bootstrap(u32 falcon_id); 38bool gm20b_is_lazy_bootstrap(u32 falcon_id);
39bool gm20b_is_priv_load(u32 falcon_id); 39bool gm20b_is_priv_load(u32 falcon_id);
40void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
41int gm20b_alloc_blob_space(struct gk20a *g, size_t size, struct nvgpu_mem *mem);
42int gm20b_pmu_populate_loader_cfg(struct gk20a *g, 40int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
43 void *lsfm, u32 *p_bl_gen_desc_size); 41 void *lsfm, u32 *p_bl_gen_desc_size);
44int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, 42int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
45 void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); 43 void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
46void gm20b_update_lspmu_cmdline_args(struct gk20a *g); 44void gm20b_update_lspmu_cmdline_args(struct gk20a *g);
47void gm20b_setup_apertures(struct gk20a *g); 45void gm20b_setup_apertures(struct gk20a *g);
48
49int gm20b_pmu_setup_sw(struct gk20a *g); 46int gm20b_pmu_setup_sw(struct gk20a *g);
50int gm20b_init_nspmu_setup_hw1(struct gk20a *g); 47int gm20b_init_nspmu_setup_hw1(struct gk20a *g);
48
51int acr_ucode_patch_sig(struct gk20a *g, 49int acr_ucode_patch_sig(struct gk20a *g,
52 unsigned int *p_img, 50 unsigned int *p_img,
53 unsigned int *p_prod_sig, 51 unsigned int *p_prod_sig,
54 unsigned int *p_dbg_sig, 52 unsigned int *p_dbg_sig,
55 unsigned int *p_patch_loc, 53 unsigned int *p_patch_loc,
56 unsigned int *p_patch_ind); 54 unsigned int *p_patch_ind);
55int gm20b_alloc_blob_space(struct gk20a *g,
56 size_t size, struct nvgpu_mem *mem);
57void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
58int gm20b_acr_patch_wpr_info_to_ucode(struct gk20a *g,
59 struct nvgpu_acr *acr, struct hs_acr *acr_desc, bool is_recovery);
60int gm20b_acr_fill_bl_dmem_desc(struct gk20a *g,
61 struct nvgpu_acr *acr, struct hs_acr *acr_desc,
62 u32 *acr_ucode_header);
63int gm20b_bootstrap_hs_acr(struct gk20a *g, struct nvgpu_acr *acr,
64 struct hs_acr *acr_desc);
65void gm20b_remove_acr_support(struct nvgpu_acr *acr);
66void nvgpu_gm20b_acr_sw_init(struct gk20a *g, struct nvgpu_acr *acr);
67
57#endif /*NVGPU_GM20B_ACR_GM20B_H*/ 68#endif /*NVGPU_GM20B_ACR_GM20B_H*/