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path: root/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
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Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/acr_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/acr_gm20b.c16
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index 50b495a6..470a93bc 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -55,13 +55,13 @@ static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm);
55 55
56/*Globals*/ 56/*Globals*/
57static void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE); 57static void __iomem *mc = IO_ADDRESS(TEGRA_MC_BASE);
58get_ucode_details pmu_acr_supp_ucode_list[] = { 58static get_ucode_details pmu_acr_supp_ucode_list[] = {
59 pmu_ucode_details, 59 pmu_ucode_details,
60 fecs_ucode_details, 60 fecs_ucode_details,
61}; 61};
62 62
63/*Once is LS mode, cpuctl_alias is only accessible*/ 63/*Once is LS mode, cpuctl_alias is only accessible*/
64void start_gm20b_pmu(struct gk20a *g) 64static void start_gm20b_pmu(struct gk20a *g)
65{ 65{
66 /*disable irqs for hs falcon booting as we will poll for halt*/ 66 /*disable irqs for hs falcon booting as we will poll for halt*/
67 mutex_lock(&g->pmu.isr_mutex); 67 mutex_lock(&g->pmu.isr_mutex);
@@ -272,7 +272,7 @@ int prepare_ucode_blob(struct gk20a *g)
272 return 0; 272 return 0;
273} 273}
274 274
275u8 lsfm_falcon_disabled(struct gk20a *g, struct ls_flcn_mgr *plsfm, 275static u8 lsfm_falcon_disabled(struct gk20a *g, struct ls_flcn_mgr *plsfm,
276 u32 falcon_id) 276 u32 falcon_id)
277{ 277{
278 return (plsfm->disable_mask >> falcon_id) & 0x1; 278 return (plsfm->disable_mask >> falcon_id) & 0x1;
@@ -364,7 +364,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g,
364} 364}
365 365
366 366
367int pmu_populate_loader_cfg(struct gk20a *g, 367static int pmu_populate_loader_cfg(struct gk20a *g,
368 struct lsfm_managed_ucode_img *lsfm, 368 struct lsfm_managed_ucode_img *lsfm,
369 union flcn_bl_generic_desc *p_bl_gen_desc, u32 *p_bl_gen_desc_size) 369 union flcn_bl_generic_desc *p_bl_gen_desc, u32 *p_bl_gen_desc_size)
370{ 370{
@@ -431,7 +431,7 @@ int pmu_populate_loader_cfg(struct gk20a *g,
431 return 0; 431 return 0;
432} 432}
433 433
434int flcn_populate_bl_dmem_desc(struct gk20a *g, 434static int flcn_populate_bl_dmem_desc(struct gk20a *g,
435 struct lsfm_managed_ucode_img *lsfm, 435 struct lsfm_managed_ucode_img *lsfm,
436 union flcn_bl_generic_desc *p_bl_gen_desc, u32 *p_bl_gen_desc_size) 436 union flcn_bl_generic_desc *p_bl_gen_desc, u32 *p_bl_gen_desc_size)
437{ 437{
@@ -1019,7 +1019,7 @@ err_release_acr_fw:
1019 return err; 1019 return err;
1020} 1020}
1021 1021
1022u8 pmu_is_debug_mode_en(struct gk20a *g) 1022static u8 pmu_is_debug_mode_en(struct gk20a *g)
1023{ 1023{
1024 u32 ctl_stat = gk20a_readl(g, pwr_pmu_scpctl_stat_r()); 1024 u32 ctl_stat = gk20a_readl(g, pwr_pmu_scpctl_stat_r());
1025 return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat); 1025 return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat);
@@ -1125,8 +1125,8 @@ static int bl_bootstrap(struct pmu_gk20a *pmu,
1125 return 0; 1125 return 0;
1126} 1126}
1127 1127
1128int gm20b_init_pmu_setup_hw1(struct gk20a *g, struct flcn_bl_dmem_desc *desc, 1128static int gm20b_init_pmu_setup_hw1(struct gk20a *g,
1129 u32 bl_sz) 1129 struct flcn_bl_dmem_desc *desc, u32 bl_sz)
1130{ 1130{
1131 1131
1132 struct pmu_gk20a *pmu = &g->pmu; 1132 struct pmu_gk20a *pmu = &g->pmu;