1 files changed, 0 insertions, 70 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index a4657ff3..e38e9a85 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -1045,76 +1045,6 @@ int acr_ucode_patch_sig(struct gk20a *g,
         return 0;
 }
 
-int gm20b_init_nspmu_setup_hw1(struct gk20a *g)
-{
-        struct nvgpu_pmu *pmu = &g->pmu;
-        int err = 0;
-
-        nvgpu_log_fn(g, " ");
-
-        nvgpu_mutex_acquire(&pmu->isr_mutex);
-        nvgpu_flcn_reset(pmu->flcn);
-        pmu->isr_enabled = true;
-        nvgpu_mutex_release(&pmu->isr_mutex);
-
-        /* setup apertures - virtual */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
-                pwr_fbif_transcfg_mem_type_virtual_f());
-        /* setup apertures - physical */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_coherent_sysmem_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
-                pwr_fbif_transcfg_mem_type_physical_f() |
-                pwr_fbif_transcfg_target_noncoherent_sysmem_f());
-
-        err = g->ops.pmu.pmu_nsbootstrap(pmu);
-
-        return err;
-}
-
-void gm20b_setup_apertures(struct gk20a *g)
-{
-        /* setup apertures - virtual */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT),
-                        pwr_fbif_transcfg_mem_type_virtual_f());
-        /* setup apertures - physical */
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_local_fb_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_coherent_sysmem_f());
-        gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH),
-                        pwr_fbif_transcfg_mem_type_physical_f() |
-                        pwr_fbif_transcfg_target_noncoherent_sysmem_f());
-}
-
-void gm20b_update_lspmu_cmdline_args(struct gk20a *g)
-{
-        struct nvgpu_pmu *pmu = &g->pmu;
-        /*Copying pmu cmdline args*/
-        g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
-                g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
-        g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
-                pmu, GK20A_PMU_TRACE_BUFSIZE);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu);
-        g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx(
-                pmu, GK20A_PMU_DMAIDX_VIRT);
-        nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args,
-                (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)),
-                g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0);
-}
-
 static int nvgpu_gm20b_acr_wait_for_completion(struct gk20a *g,
         struct nvgpu_falcon *flcn, unsigned int timeout)
 {