diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm206')
-rw-r--r-- | drivers/gpu/nvgpu/gm206/ce_gm206.c | 107 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/ce_gm206.h | 26 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/fifo_gm206.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/hal_gm206.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/hw_proj_gm206.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/hw_top_gm206.h | 16 |
6 files changed, 160 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm206/ce_gm206.c b/drivers/gpu/nvgpu/gm206/ce_gm206.c new file mode 100644 index 00000000..9ec42831 --- /dev/null +++ b/drivers/gpu/nvgpu/gm206/ce_gm206.c | |||
@@ -0,0 +1,107 @@ | |||
1 | /* | ||
2 | * GM206 Copy Engine. | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along with | ||
16 | * this program. | ||
17 | */ | ||
18 | |||
19 | /*TODO: remove uncecessary */ | ||
20 | #include "gk20a/gk20a.h" | ||
21 | #include "ce_gm206.h" | ||
22 | |||
23 | /*TODO: remove uncecessary */ | ||
24 | #include <linux/delay.h> | ||
25 | #include <linux/slab.h> | ||
26 | #include <linux/scatterlist.h> | ||
27 | #include <trace/events/gk20a.h> | ||
28 | #include <linux/dma-mapping.h> | ||
29 | #include <linux/nvhost.h> | ||
30 | |||
31 | #include "gk20a/debug_gk20a.h" | ||
32 | #include "gk20a/semaphore_gk20a.h" | ||
33 | #include "hw_ce2_gm206.h" | ||
34 | #include "hw_pbdma_gm206.h" | ||
35 | #include "hw_ccsr_gm206.h" | ||
36 | #include "hw_ram_gm206.h" | ||
37 | #include "hw_top_gm206.h" | ||
38 | #include "hw_mc_gm206.h" | ||
39 | #include "hw_gr_gm206.h" | ||
40 | |||
41 | /* TODO: We need generic way for query the intr_status register offset. | ||
42 | * As of now, there is no way to query this information from dev_ceN_pri.h */ | ||
43 | #define COP_INTR_STATUS_OFFSET 0x908 | ||
44 | |||
45 | static u32 ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id) | ||
46 | { | ||
47 | gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n"); | ||
48 | |||
49 | return ce2_intr_status_nonblockpipe_pending_f(); | ||
50 | } | ||
51 | |||
52 | static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id) | ||
53 | { | ||
54 | gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n"); | ||
55 | |||
56 | return ce2_intr_status_blockpipe_pending_f(); | ||
57 | } | ||
58 | |||
59 | static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id) | ||
60 | { | ||
61 | gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n"); | ||
62 | |||
63 | return ce2_intr_status_launcherr_pending_f(); | ||
64 | } | ||
65 | |||
66 | void gm206_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | ||
67 | { | ||
68 | u32 ce_intr_status_reg = (pri_base + COP_INTR_STATUS_OFFSET); | ||
69 | u32 ce_intr = gk20a_readl(g, ce_intr_status_reg); | ||
70 | u32 clear_intr = 0; | ||
71 | |||
72 | gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id); | ||
73 | |||
74 | /* clear blocking interrupts: they exibit broken behavior */ | ||
75 | if (ce_intr & ce2_intr_status_blockpipe_pending_f()) | ||
76 | clear_intr |= ce_blockpipe_isr(g, ce_intr, inst_id); | ||
77 | |||
78 | if (ce_intr & ce2_intr_status_launcherr_pending_f()) | ||
79 | clear_intr |= ce_launcherr_isr(g, ce_intr, inst_id); | ||
80 | |||
81 | gk20a_writel(g, ce_intr_status_reg, clear_intr); | ||
82 | return; | ||
83 | } | ||
84 | |||
85 | void gm206_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | ||
86 | { | ||
87 | u32 ce_intr_status_reg = (pri_base + COP_INTR_STATUS_OFFSET); | ||
88 | u32 ce_intr = gk20a_readl(g, ce_intr_status_reg); | ||
89 | |||
90 | gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); | ||
91 | |||
92 | if (ce_intr & ce2_intr_status_nonblockpipe_pending_f()) { | ||
93 | gk20a_writel(g, ce_intr_status_reg, | ||
94 | ce_nonblockpipe_isr(g, ce_intr, inst_id)); | ||
95 | |||
96 | /* wake threads waiting in this channel */ | ||
97 | gk20a_channel_semaphore_wakeup(g, true); | ||
98 | } | ||
99 | |||
100 | return; | ||
101 | } | ||
102 | |||
103 | void gm206_init_ce(struct gpu_ops *gops) | ||
104 | { | ||
105 | gops->ce2.isr_stall = gm206_ce_isr; | ||
106 | gops->ce2.isr_nonstall = gm206_ce_nonstall_isr; | ||
107 | } | ||
diff --git a/drivers/gpu/nvgpu/gm206/ce_gm206.h b/drivers/gpu/nvgpu/gm206/ce_gm206.h new file mode 100644 index 00000000..c2fb1586 --- /dev/null +++ b/drivers/gpu/nvgpu/gm206/ce_gm206.h | |||
@@ -0,0 +1,26 @@ | |||
1 | /* | ||
2 | * GM206 copy engine. | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along with | ||
16 | * this program. | ||
17 | */ | ||
18 | #ifndef __CE_GM206_H__ | ||
19 | #define __CE_GM206_H__ | ||
20 | |||
21 | #include "gk20a/channel_gk20a.h" | ||
22 | #include "gk20a/tsg_gk20a.h" | ||
23 | |||
24 | void gm206_init_ce(struct gpu_ops *gops); | ||
25 | |||
26 | #endif /*__CE2_GM20B_H__*/ | ||
diff --git a/drivers/gpu/nvgpu/gm206/fifo_gm206.c b/drivers/gpu/nvgpu/gm206/fifo_gm206.c index c78f256c..6caf30f4 100644 --- a/drivers/gpu/nvgpu/gm206/fifo_gm206.c +++ b/drivers/gpu/nvgpu/gm206/fifo_gm206.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include "gm20b/fifo_gm20b.h" | 18 | #include "gm20b/fifo_gm20b.h" |
19 | #include "fifo_gm206.h" | 19 | #include "fifo_gm206.h" |
20 | #include "hw_ccsr_gm206.h" | 20 | #include "hw_ccsr_gm206.h" |
21 | #include "hw_fifo_gm206.h" | ||
21 | 22 | ||
22 | static u32 gm206_fifo_get_num_fifos(struct gk20a *g) | 23 | static u32 gm206_fifo_get_num_fifos(struct gk20a *g) |
23 | { | 24 | { |
@@ -28,4 +29,5 @@ void gm206_init_fifo(struct gpu_ops *gops) | |||
28 | { | 29 | { |
29 | gm20b_init_fifo(gops); | 30 | gm20b_init_fifo(gops); |
30 | gops->fifo.get_num_fifos = gm206_fifo_get_num_fifos; | 31 | gops->fifo.get_num_fifos = gm206_fifo_get_num_fifos; |
32 | gops->fifo.eng_runlist_base_size = fifo_eng_runlist_base__size_1_v; | ||
31 | } | 33 | } |
diff --git a/drivers/gpu/nvgpu/gm206/hal_gm206.c b/drivers/gpu/nvgpu/gm206/hal_gm206.c index 048a109f..6b5c70e2 100644 --- a/drivers/gpu/nvgpu/gm206/hal_gm206.c +++ b/drivers/gpu/nvgpu/gm206/hal_gm206.c | |||
@@ -21,7 +21,7 @@ | |||
21 | #include "gm20b/mc_gm20b.h" | 21 | #include "gm20b/mc_gm20b.h" |
22 | #include "gm20b/ltc_gm20b.h" | 22 | #include "gm20b/ltc_gm20b.h" |
23 | #include "gm20b/mm_gm20b.h" | 23 | #include "gm20b/mm_gm20b.h" |
24 | #include "gm20b/ce2_gm20b.h" | 24 | #include "ce_gm206.h" |
25 | #include "gm20b/fb_gm20b.h" | 25 | #include "gm20b/fb_gm20b.h" |
26 | #include "gm20b/pmu_gm20b.h" | 26 | #include "gm20b/pmu_gm20b.h" |
27 | #include "gm20b/gr_gm20b.h" | 27 | #include "gm20b/gr_gm20b.h" |
@@ -142,6 +142,9 @@ static int gm206_get_litter_value(struct gk20a *g, | |||
142 | case GPU_LIT_ROP_SHARED_BASE: | 142 | case GPU_LIT_ROP_SHARED_BASE: |
143 | ret = proj_rop_shared_base_v(); | 143 | ret = proj_rop_shared_base_v(); |
144 | break; | 144 | break; |
145 | case GPU_LIT_HOST_NUM_ENGINES: | ||
146 | ret = proj_host_num_engines_v(); | ||
147 | break; | ||
145 | case GPU_LIT_HOST_NUM_PBDMA: | 148 | case GPU_LIT_HOST_NUM_PBDMA: |
146 | ret = proj_host_num_pbdma_v(); | 149 | ret = proj_host_num_pbdma_v(); |
147 | break; | 150 | break; |
@@ -183,7 +186,7 @@ int gm206_init_hal(struct gk20a *g) | |||
183 | gm20b_init_fb(gops); | 186 | gm20b_init_fb(gops); |
184 | g->ops.fb.set_use_full_comp_tag_line = NULL; | 187 | g->ops.fb.set_use_full_comp_tag_line = NULL; |
185 | gm206_init_fifo(gops); | 188 | gm206_init_fifo(gops); |
186 | gm20b_init_ce2(gops); | 189 | gm206_init_ce(gops); |
187 | gm20b_init_gr_ctx(gops); | 190 | gm20b_init_gr_ctx(gops); |
188 | gm20b_init_mm(gops); | 191 | gm20b_init_mm(gops); |
189 | gm206_init_pmu_ops(gops); | 192 | gm206_init_pmu_ops(gops); |
diff --git a/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h b/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h index 2f4187d0..6c21b39a 100644 --- a/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h +++ b/drivers/gpu/nvgpu/gm206/hw_proj_gm206.h | |||
@@ -106,6 +106,10 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void) | |||
106 | { | 106 | { |
107 | return 0x00001800; | 107 | return 0x00001800; |
108 | } | 108 | } |
109 | static inline u32 proj_host_num_engines_v(void) | ||
110 | { | ||
111 | return 0x00000008; | ||
112 | } | ||
109 | static inline u32 proj_host_num_pbdma_v(void) | 113 | static inline u32 proj_host_num_pbdma_v(void) |
110 | { | 114 | { |
111 | return 0x00000003; | 115 | return 0x00000003; |
diff --git a/drivers/gpu/nvgpu/gm206/hw_top_gm206.h b/drivers/gpu/nvgpu/gm206/hw_top_gm206.h index e6ec1d27..988f24ea 100644 --- a/drivers/gpu/nvgpu/gm206/hw_top_gm206.h +++ b/drivers/gpu/nvgpu/gm206/hw_top_gm206.h | |||
@@ -146,6 +146,22 @@ static inline u32 top_device_info_type_enum_copy0_f(void) | |||
146 | { | 146 | { |
147 | return 0x4; | 147 | return 0x4; |
148 | } | 148 | } |
149 | static inline u32 top_device_info_type_enum_copy1_v(void) | ||
150 | { | ||
151 | return 0x00000002; | ||
152 | } | ||
153 | static inline u32 top_device_info_type_enum_copy1_f(void) | ||
154 | { | ||
155 | return 0x8; | ||
156 | } | ||
157 | static inline u32 top_device_info_type_enum_copy2_v(void) | ||
158 | { | ||
159 | return 0x00000003; | ||
160 | } | ||
161 | static inline u32 top_device_info_type_enum_copy2_f(void) | ||
162 | { | ||
163 | return 0xc; | ||
164 | } | ||
149 | static inline u32 top_device_info_entry_v(u32 r) | 165 | static inline u32 top_device_info_entry_v(u32 r) |
150 | { | 166 | { |
151 | return (r >> 0) & 0x3; | 167 | return (r >> 0) & 0x3; |