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Diffstat (limited to 'drivers/gpu/nvgpu/gm206/hal_gm206.c')
-rw-r--r--drivers/gpu/nvgpu/gm206/hal_gm206.c206
1 files changed, 206 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm206/hal_gm206.c b/drivers/gpu/nvgpu/gm206/hal_gm206.c
new file mode 100644
index 00000000..aa6b676f
--- /dev/null
+++ b/drivers/gpu/nvgpu/gm206/hal_gm206.c
@@ -0,0 +1,206 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <linux/types.h>
15#include <linux/printk.h>
16
17#include <linux/types.h>
18
19#include "gk20a/gk20a.h"
20
21#include "gm20b/mc_gm20b.h"
22#include "gm20b/ltc_gm20b.h"
23#include "gm20b/mm_gm20b.h"
24#include "gm20b/ce2_gm20b.h"
25#include "gm20b/fb_gm20b.h"
26#include "gm20b/pmu_gm20b.h"
27#include "gm20b/gr_gm20b.h"
28#include "gm20b/gr_ctx_gm20b.h"
29#include "gm20b/gm20b_gating_reglist.h"
30#include "gm20b/regops_gm20b.h"
31#include "gm20b/cde_gm20b.h"
32#include "gm20b/therm_gm20b.h"
33#include "gm20b/clk_gm20b.h"
34#include "gm20b/debug_gm20b.h"
35
36#include "fifo_gm206.h"
37#include "bios_gm206.h"
38#include "gr_gm206.h"
39#include "hw_proj_gm206.h"
40
41static struct gpu_ops gm206_ops = {
42 .clock_gating = {
43 .slcg_bus_load_gating_prod =
44 gm20b_slcg_bus_load_gating_prod,
45 .slcg_ce2_load_gating_prod =
46 gm20b_slcg_ce2_load_gating_prod,
47 .slcg_chiplet_load_gating_prod =
48 gm20b_slcg_chiplet_load_gating_prod,
49 .slcg_ctxsw_firmware_load_gating_prod =
50 gm20b_slcg_ctxsw_firmware_load_gating_prod,
51 .slcg_fb_load_gating_prod =
52 gm20b_slcg_fb_load_gating_prod,
53 .slcg_fifo_load_gating_prod =
54 gm20b_slcg_fifo_load_gating_prod,
55 .slcg_gr_load_gating_prod =
56 gr_gm20b_slcg_gr_load_gating_prod,
57 .slcg_ltc_load_gating_prod =
58 ltc_gm20b_slcg_ltc_load_gating_prod,
59 .slcg_perf_load_gating_prod =
60 gm20b_slcg_perf_load_gating_prod,
61 .slcg_priring_load_gating_prod =
62 gm20b_slcg_priring_load_gating_prod,
63 .slcg_pmu_load_gating_prod =
64 gm20b_slcg_pmu_load_gating_prod,
65 .slcg_therm_load_gating_prod =
66 gm20b_slcg_therm_load_gating_prod,
67 .slcg_xbar_load_gating_prod =
68 gm20b_slcg_xbar_load_gating_prod,
69 .blcg_bus_load_gating_prod =
70 gm20b_blcg_bus_load_gating_prod,
71 .blcg_ctxsw_firmware_load_gating_prod =
72 gm20b_blcg_ctxsw_firmware_load_gating_prod,
73 .blcg_fb_load_gating_prod =
74 gm20b_blcg_fb_load_gating_prod,
75 .blcg_fifo_load_gating_prod =
76 gm20b_blcg_fifo_load_gating_prod,
77 .blcg_gr_load_gating_prod =
78 gm20b_blcg_gr_load_gating_prod,
79 .blcg_ltc_load_gating_prod =
80 gm20b_blcg_ltc_load_gating_prod,
81 .blcg_pwr_csb_load_gating_prod =
82 gm20b_blcg_pwr_csb_load_gating_prod,
83 .blcg_pmu_load_gating_prod =
84 gm20b_blcg_pmu_load_gating_prod,
85 .blcg_xbar_load_gating_prod =
86 gm20b_blcg_xbar_load_gating_prod,
87 .pg_gr_load_gating_prod =
88 gr_gm20b_pg_gr_load_gating_prod,
89 }
90};
91
92static int gm206_get_litter_value(struct gk20a *g,
93 enum nvgpu_litter_value value)
94{
95 int ret = -EINVAL;
96
97 switch (value) {
98 case GPU_LIT_NUM_GPCS:
99 ret = proj_scal_litter_num_gpcs_v();
100 break;
101 case GPU_LIT_NUM_PES_PER_GPC:
102 ret = proj_scal_litter_num_pes_per_gpc_v();
103 break;
104 case GPU_LIT_NUM_ZCULL_BANKS:
105 ret = proj_scal_litter_num_zcull_banks_v();
106 break;
107 case GPU_LIT_NUM_TPC_PER_GPC:
108 ret = proj_scal_litter_num_tpc_per_gpc_v();
109 break;
110 case GPU_LIT_NUM_FBPS:
111 ret = proj_scal_litter_num_fbps_v();
112 break;
113 case GPU_LIT_GPC_BASE:
114 ret = proj_gpc_base_v();
115 break;
116 case GPU_LIT_GPC_STRIDE:
117 ret = proj_gpc_stride_v();
118 break;
119 case GPU_LIT_GPC_SHARED_BASE:
120 ret = proj_gpc_shared_base_v();
121 break;
122 case GPU_LIT_TPC_IN_GPC_BASE:
123 ret = proj_tpc_in_gpc_base_v();
124 break;
125 case GPU_LIT_TPC_IN_GPC_STRIDE:
126 ret = proj_tpc_in_gpc_stride_v();
127 break;
128 case GPU_LIT_TPC_IN_GPC_SHARED_BASE:
129 ret = proj_tpc_in_gpc_shared_base_v();
130 break;
131 case GPU_LIT_PPC_IN_GPC_STRIDE:
132 ret = proj_ppc_in_gpc_stride_v();
133 break;
134 case GPU_LIT_ROP_BASE:
135 ret = proj_rop_base_v();
136 break;
137 case GPU_LIT_ROP_STRIDE:
138 ret = proj_rop_stride_v();
139 break;
140 case GPU_LIT_ROP_SHARED_BASE:
141 ret = proj_rop_shared_base_v();
142 break;
143 case GPU_LIT_HOST_NUM_PBDMA:
144 ret = proj_host_num_pbdma_v();
145 break;
146 case GPU_LIT_LTC_STRIDE:
147 ret = proj_ltc_stride_v();
148 break;
149 case GPU_LIT_LTS_STRIDE:
150 ret = proj_lts_stride_v();
151 break;
152 case GPU_LIT_NUM_FBPAS:
153 ret = proj_scal_litter_num_fbpas_v();
154 break;
155 case GPU_LIT_FBPA_STRIDE:
156 ret = proj_fbpa_stride_v();
157 break;
158 default:
159 BUG();
160 break;
161 }
162
163 return ret;
164}
165
166int gm206_init_hal(struct gk20a *g)
167{
168 struct gpu_ops *gops = &g->ops;
169 struct nvgpu_gpu_characteristics *c = &g->gpu_characteristics;
170
171 *gops = gm206_ops;
172
173 gops->privsecurity = 0;
174 gops->securegpccs = 0;
175
176 gm20b_init_mc(gops);
177 gm20b_init_ltc(gops);
178 gm206_init_gr(gops);
179 gm20b_init_ltc(gops);
180 gm20b_init_fb(gops);
181 g->ops.fb.set_use_full_comp_tag_line = NULL;
182 gm206_init_fifo(gops);
183 gm20b_init_ce2(gops);
184 gm20b_init_gr_ctx(gops);
185 gm20b_init_mm(gops);
186 gm20b_init_pmu_ops(gops);
187 gm20b_init_clk_ops(gops);
188 gm20b_init_regops(gops);
189 gm20b_init_debug_ops(gops);
190 gm20b_init_cde_ops(gops);
191 gm20b_init_therm_ops(gops);
192 gm206_init_bios(gops);
193 gops->name = "gm206";
194 gops->chip_init_gpu_characteristics = gk20a_init_gpu_characteristics;
195 gops->get_litter_value = gm206_get_litter_value;
196 gops->gr_ctx.use_dma_for_fw_bootstrap = false;
197
198 c->twod_class = FERMI_TWOD_A;
199 c->threed_class = MAXWELL_B;
200 c->compute_class = MAXWELL_COMPUTE_B;
201 c->gpfifo_class = MAXWELL_CHANNEL_GPFIFO_A;
202 c->inline_to_memory_class = KEPLER_INLINE_TO_MEMORY_B;
203 c->dma_copy_class = MAXWELL_DMA_COPY_A;
204
205 return 0;
206}
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 20:59:02 -0400