diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gm206/ce_gm206.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm206/ce_gm206.c | 107 |
1 files changed, 0 insertions, 107 deletions
diff --git a/drivers/gpu/nvgpu/gm206/ce_gm206.c b/drivers/gpu/nvgpu/gm206/ce_gm206.c deleted file mode 100644 index dd3eac95..00000000 --- a/drivers/gpu/nvgpu/gm206/ce_gm206.c +++ /dev/null | |||
@@ -1,107 +0,0 @@ | |||
1 | /* | ||
2 | * GM206 Copy Engine. | ||
3 | * | ||
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along with | ||
16 | * this program. | ||
17 | */ | ||
18 | |||
19 | /*TODO: remove uncecessary */ | ||
20 | #include "gk20a/gk20a.h" | ||
21 | #include "ce_gm206.h" | ||
22 | |||
23 | /*TODO: remove uncecessary */ | ||
24 | #include <linux/delay.h> | ||
25 | #include <linux/slab.h> | ||
26 | #include <linux/scatterlist.h> | ||
27 | #include <trace/events/gk20a.h> | ||
28 | #include <linux/dma-mapping.h> | ||
29 | #include <linux/nvhost.h> | ||
30 | |||
31 | #include "gk20a/debug_gk20a.h" | ||
32 | |||
33 | #include <nvgpu/hw/gm206/hw_ce2_gm206.h> | ||
34 | #include <nvgpu/hw/gm206/hw_pbdma_gm206.h> | ||
35 | #include <nvgpu/hw/gm206/hw_ccsr_gm206.h> | ||
36 | #include <nvgpu/hw/gm206/hw_ram_gm206.h> | ||
37 | #include <nvgpu/hw/gm206/hw_top_gm206.h> | ||
38 | #include <nvgpu/hw/gm206/hw_mc_gm206.h> | ||
39 | #include <nvgpu/hw/gm206/hw_gr_gm206.h> | ||
40 | |||
41 | /* TODO: We need generic way for query the intr_status register offset. | ||
42 | * As of now, there is no way to query this information from dev_ceN_pri.h */ | ||
43 | #define COP_INTR_STATUS_OFFSET 0x908 | ||
44 | |||
45 | static u32 ce_nonblockpipe_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id) | ||
46 | { | ||
47 | gk20a_dbg(gpu_dbg_intr, "ce non-blocking pipe interrupt\n"); | ||
48 | |||
49 | return ce2_intr_status_nonblockpipe_pending_f(); | ||
50 | } | ||
51 | |||
52 | static u32 ce_blockpipe_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id) | ||
53 | { | ||
54 | gk20a_dbg(gpu_dbg_intr, "ce blocking pipe interrupt\n"); | ||
55 | |||
56 | return ce2_intr_status_blockpipe_pending_f(); | ||
57 | } | ||
58 | |||
59 | static u32 ce_launcherr_isr(struct gk20a *g, u32 fifo_intr, u32 inst_id) | ||
60 | { | ||
61 | gk20a_dbg(gpu_dbg_intr, "ce launch error interrupt\n"); | ||
62 | |||
63 | return ce2_intr_status_launcherr_pending_f(); | ||
64 | } | ||
65 | |||
66 | static void gm206_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | ||
67 | { | ||
68 | u32 ce_intr_status_reg = (pri_base + COP_INTR_STATUS_OFFSET); | ||
69 | u32 ce_intr = gk20a_readl(g, ce_intr_status_reg); | ||
70 | u32 clear_intr = 0; | ||
71 | |||
72 | gk20a_dbg(gpu_dbg_intr, "ce isr %08x %08x\n", ce_intr, inst_id); | ||
73 | |||
74 | /* clear blocking interrupts: they exibit broken behavior */ | ||
75 | if (ce_intr & ce2_intr_status_blockpipe_pending_f()) | ||
76 | clear_intr |= ce_blockpipe_isr(g, ce_intr, inst_id); | ||
77 | |||
78 | if (ce_intr & ce2_intr_status_launcherr_pending_f()) | ||
79 | clear_intr |= ce_launcherr_isr(g, ce_intr, inst_id); | ||
80 | |||
81 | gk20a_writel(g, ce_intr_status_reg, clear_intr); | ||
82 | return; | ||
83 | } | ||
84 | |||
85 | static void gm206_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | ||
86 | { | ||
87 | u32 ce_intr_status_reg = (pri_base + COP_INTR_STATUS_OFFSET); | ||
88 | u32 ce_intr = gk20a_readl(g, ce_intr_status_reg); | ||
89 | |||
90 | gk20a_dbg(gpu_dbg_intr, "ce nonstall isr %08x %08x\n", ce_intr, inst_id); | ||
91 | |||
92 | if (ce_intr & ce2_intr_status_nonblockpipe_pending_f()) { | ||
93 | gk20a_writel(g, ce_intr_status_reg, | ||
94 | ce_nonblockpipe_isr(g, ce_intr, inst_id)); | ||
95 | |||
96 | /* wake threads waiting in this channel */ | ||
97 | gk20a_channel_semaphore_wakeup(g, true); | ||
98 | } | ||
99 | |||
100 | return; | ||
101 | } | ||
102 | |||
103 | void gm206_init_ce(struct gpu_ops *gops) | ||
104 | { | ||
105 | gops->ce2.isr_stall = gm206_ce_isr; | ||
106 | gops->ce2.isr_nonstall = gm206_ce_nonstall_isr; | ||
107 | } | ||