diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 28 |
2 files changed, 39 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index b4886e31..868792c0 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -186,6 +186,18 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
186 | } | 186 | } |
187 | } | 187 | } |
188 | 188 | ||
189 | if (nvgpu_is_enabled(g, NVGPU_SUPPORT_NVLINK)) { | ||
190 | if (g->ops.nvlink.init) { | ||
191 | err = g->ops.nvlink.init(g); | ||
192 | if (err) { | ||
193 | nvgpu_err(g, "failed to init nvlink"); | ||
194 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, | ||
195 | false); | ||
196 | } | ||
197 | } else | ||
198 | __nvgpu_set_enabled(g, NVGPU_SUPPORT_NVLINK, false); | ||
199 | } | ||
200 | |||
189 | if (g->ops.fb.mem_unlock) { | 201 | if (g->ops.fb.mem_unlock) { |
190 | err = g->ops.fb.mem_unlock(g); | 202 | err = g->ops.fb.mem_unlock(g); |
191 | if (err) { | 203 | if (err) { |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index cc62865c..f187f730 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -62,6 +62,7 @@ struct nvgpu_ctxsw_trace_filter; | |||
62 | #include <nvgpu/barrier.h> | 62 | #include <nvgpu/barrier.h> |
63 | #include <nvgpu/rwsem.h> | 63 | #include <nvgpu/rwsem.h> |
64 | #include <nvgpu/clk_arb.h> | 64 | #include <nvgpu/clk_arb.h> |
65 | #include <nvgpu/nvlink.h> | ||
65 | 66 | ||
66 | #include "clk_gk20a.h" | 67 | #include "clk_gk20a.h" |
67 | #include "ce2_gk20a.h" | 68 | #include "ce2_gk20a.h" |
@@ -961,6 +962,7 @@ struct gpu_ops { | |||
961 | bool enable, bool is_stalling, u32 unit); | 962 | bool enable, bool is_stalling, u32 unit); |
962 | void (*isr_stall)(struct gk20a *g); | 963 | void (*isr_stall)(struct gk20a *g); |
963 | bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr); | 964 | bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr); |
965 | bool (*is_intr_nvlink_pending)(struct gk20a *g, u32 mc_intr); | ||
964 | u32 (*intr_stall)(struct gk20a *g); | 966 | u32 (*intr_stall)(struct gk20a *g); |
965 | void (*intr_stall_pause)(struct gk20a *g); | 967 | void (*intr_stall_pause)(struct gk20a *g); |
966 | void (*intr_stall_resume)(struct gk20a *g); | 968 | void (*intr_stall_resume)(struct gk20a *g); |
@@ -1057,7 +1059,27 @@ struct gpu_ops { | |||
1057 | struct { | 1059 | struct { |
1058 | int (*check_priv_security)(struct gk20a *g); | 1060 | int (*check_priv_security)(struct gk20a *g); |
1059 | } fuse; | 1061 | } fuse; |
1060 | 1062 | struct { | |
1063 | u32 (*init)(struct gk20a *g); | ||
1064 | u32 (*discover_ioctrl)(struct gk20a *g); | ||
1065 | u32 (*discover_link)(struct gk20a *g); | ||
1066 | u32 (*isr)(struct gk20a *g); | ||
1067 | /* API */ | ||
1068 | int (*link_early_init)(struct gk20a *g, unsigned long mask); | ||
1069 | u32 (*link_get_mode)(struct gk20a *g, u32 link_id); | ||
1070 | u32 (*link_get_state)(struct gk20a *g, u32 link_id); | ||
1071 | int (*link_set_mode)(struct gk20a *g, u32 link_id, u32 mode); | ||
1072 | u32 (*get_sublink_mode)(struct gk20a *g, u32 link_id, | ||
1073 | bool is_rx_sublink); | ||
1074 | u32 (*get_rx_sublink_state)(struct gk20a *g, u32 link_id); | ||
1075 | u32 (*get_tx_sublink_state)(struct gk20a *g, u32 link_id); | ||
1076 | int (*set_sublink_mode)(struct gk20a *g, u32 link_id, | ||
1077 | bool is_rx_sublink, u32 mode); | ||
1078 | int (*interface_init)(struct gk20a *g); | ||
1079 | int (*reg_init)(struct gk20a *g); | ||
1080 | int (*shutdown)(struct gk20a *g); | ||
1081 | int (*early_init)(struct gk20a *g); | ||
1082 | } nvlink; | ||
1061 | }; | 1083 | }; |
1062 | 1084 | ||
1063 | struct nvgpu_bios_ucode { | 1085 | struct nvgpu_bios_ucode { |
@@ -1100,6 +1122,8 @@ struct nvgpu_bios { | |||
1100 | struct bit_token *clock_token; | 1122 | struct bit_token *clock_token; |
1101 | struct bit_token *virt_token; | 1123 | struct bit_token *virt_token; |
1102 | u32 expansion_rom_offset; | 1124 | u32 expansion_rom_offset; |
1125 | |||
1126 | u32 nvlink_config_data_offset; | ||
1103 | }; | 1127 | }; |
1104 | 1128 | ||
1105 | struct nvgpu_gpu_params { | 1129 | struct nvgpu_gpu_params { |
@@ -1153,8 +1177,10 @@ struct gk20a { | |||
1153 | struct nvgpu_falcon fecs_flcn; | 1177 | struct nvgpu_falcon fecs_flcn; |
1154 | struct nvgpu_falcon gpccs_flcn; | 1178 | struct nvgpu_falcon gpccs_flcn; |
1155 | struct nvgpu_falcon nvdec_flcn; | 1179 | struct nvgpu_falcon nvdec_flcn; |
1180 | struct nvgpu_falcon minion_flcn; | ||
1156 | struct clk_gk20a clk; | 1181 | struct clk_gk20a clk; |
1157 | struct fifo_gk20a fifo; | 1182 | struct fifo_gk20a fifo; |
1183 | struct nvgpu_nvlink_dev nvlink; | ||
1158 | struct gr_gk20a gr; | 1184 | struct gr_gk20a gr; |
1159 | struct sim_gk20a *sim; | 1185 | struct sim_gk20a *sim; |
1160 | struct mm_gk20a mm; | 1186 | struct mm_gk20a mm; |