3 files changed, 0 insertions, 47 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index f802cd56..1fe0cb5d 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -437,7 +437,6 @@ struct gpu_ops {
                 void (*set_preemption_buffer_va)(struct gk20a *g,
                                         struct nvgpu_mem *mem, u64 gpu_va);
                 void (*load_tpc_mask)(struct gk20a *g);
-                int (*inval_icache)(struct gk20a *g, struct channel_gk20a *ch);
                 int (*trigger_suspend)(struct gk20a *g);
                 int (*wait_for_pause)(struct gk20a *g, struct nvgpu_warpstate *w_state);
                 int (*resume_from_pause)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index fbba02ca..90643971 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -8549,51 +8549,6 @@ clean_up:
         return err;
 }
 
-int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch)
-{
-        int err = 0;
-        u32     cache_ctrl, regval;
-        struct nvgpu_dbg_reg_op ops;
-
-        ops.op     = REGOP(READ_32);
-        ops.type   = REGOP(TYPE_GR_CTX);
-        ops.status = REGOP(STATUS_SUCCESS);
-        ops.value_hi      = 0;
-        ops.and_n_mask_lo = 0;
-        ops.and_n_mask_hi = 0;
-        ops.offset       = gr_pri_gpc0_gcc_dbg_r();
-
-        err = gr_gk20a_exec_ctx_ops(ch, &ops, 1, 0, 1);
-        if (err) {
-                nvgpu_err(g, "Failed to read register");
-                return err;
-        }
-
-        regval = ops.value_lo;
-
-        ops.op = REGOP(WRITE_32);
-        ops.value_lo = set_field(regval, gr_pri_gpcs_gcc_dbg_invalidate_m(), 1);
-        err = gr_gk20a_exec_ctx_ops(ch, &ops, 1, 1, 0);
-        if (err) {
-                nvgpu_err(g, "Failed to write register");
-                return err;
-        }
-
-        ops.op     = REGOP(READ_32);
-        ops.offset = gr_pri_gpc0_tpc0_sm_cache_control_r();
-        err = gr_gk20a_exec_ctx_ops(ch, &ops, 1, 0, 1);
-        if (err) {
-                nvgpu_err(g, "Failed to read register");
-                return err;
-        }
-
-        cache_ctrl = gk20a_readl(g, gr_pri_gpc0_tpc0_sm_cache_control_r());
-        cache_ctrl = set_field(cache_ctrl, gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(), 1);
-        gk20a_writel(g, gr_pri_gpc0_tpc0_sm_cache_control_r(), cache_ctrl);
-
-        return 0;
-}
-
 int gr_gk20a_trigger_suspend(struct gk20a *g)
 {
         int err = 0;
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 9c9a3caa..a60f6f12 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -775,7 +775,6 @@ int gr_gk20a_resume_contexts(struct gk20a *g,
                               int *ctx_resident_ch_fd);
 void gk20a_gr_enable_gpc_exceptions(struct gk20a *g);
 void gk20a_gr_enable_exceptions(struct gk20a *g);
-int gr_gk20a_inval_icache(struct gk20a *g, struct channel_gk20a *ch);
 int gr_gk20a_trigger_suspend(struct gk20a *g);
 int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state);
 int gr_gk20a_resume_from_pause(struct gk20a *g);