diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ecc_gk20a.h | 46 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hal.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | 11 |
10 files changed, 63 insertions, 78 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 371793ef..2949c426 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics channel | 2 | * GK20A Graphics channel |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -700,10 +700,8 @@ struct channel_gk20a *gk20a_open_new_channel(struct gk20a *g, | |||
700 | ch->has_timedout = false; | 700 | ch->has_timedout = false; |
701 | ch->wdt_enabled = true; | 701 | ch->wdt_enabled = true; |
702 | ch->obj_class = 0; | 702 | ch->obj_class = 0; |
703 | #ifdef CONFIG_TEGRA_19x_GPU | 703 | ch->subctx_id = 0; |
704 | memset(&ch->t19x, 0, sizeof(struct channel_t19x)); | 704 | ch->runqueue_sel = 0; |
705 | #endif | ||
706 | |||
707 | 705 | ||
708 | /* The channel is *not* runnable at this point. It still needs to have | 706 | /* The channel is *not* runnable at this point. It still needs to have |
709 | * an address space bound and allocate a gpfifo and grctx. */ | 707 | * an address space bound and allocate a gpfifo and grctx. */ |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 29fa302f..db1404a3 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A graphics channel | 2 | * GK20A graphics channel |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -40,9 +40,6 @@ struct fifo_profile_gk20a; | |||
40 | #include "mm_gk20a.h" | 40 | #include "mm_gk20a.h" |
41 | #include "gr_gk20a.h" | 41 | #include "gr_gk20a.h" |
42 | #include "fence_gk20a.h" | 42 | #include "fence_gk20a.h" |
43 | #ifdef CONFIG_TEGRA_19x_GPU | ||
44 | #include "channel_t19x.h" | ||
45 | #endif | ||
46 | 43 | ||
47 | /* Flags to be passed to gk20a_channel_alloc_gpfifo() */ | 44 | /* Flags to be passed to gk20a_channel_alloc_gpfifo() */ |
48 | #define NVGPU_GPFIFO_FLAGS_SUPPORT_VPR (1 << 0) | 45 | #define NVGPU_GPFIFO_FLAGS_SUPPORT_VPR (1 << 0) |
@@ -237,9 +234,8 @@ struct channel_gk20a { | |||
237 | u32 runlist_id; | 234 | u32 runlist_id; |
238 | 235 | ||
239 | bool is_privileged_channel; | 236 | bool is_privileged_channel; |
240 | #ifdef CONFIG_TEGRA_19x_GPU | 237 | u32 subctx_id; |
241 | struct channel_t19x t19x; | 238 | u32 runqueue_sel; |
242 | #endif | ||
243 | 239 | ||
244 | struct ctx_header_desc ctx_header; | 240 | struct ctx_header_desc ctx_header; |
245 | 241 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h index 57eec1e0..fba8ba7d 100644 --- a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A ECC | 2 | * GK20A ECC |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -33,10 +33,6 @@ struct gk20a_ecc_stat { | |||
33 | #endif | 33 | #endif |
34 | }; | 34 | }; |
35 | 35 | ||
36 | #ifdef CONFIG_TEGRA_19x_GPU | ||
37 | #include "ecc_t19x.h" | ||
38 | #endif | ||
39 | |||
40 | struct ecc_gk20a { | 36 | struct ecc_gk20a { |
41 | /* Stats per engine */ | 37 | /* Stats per engine */ |
42 | struct { | 38 | struct { |
@@ -56,24 +52,44 @@ struct ecc_gk20a { | |||
56 | struct gk20a_ecc_stat tex_unique_sec_pipe1_count; | 52 | struct gk20a_ecc_stat tex_unique_sec_pipe1_count; |
57 | struct gk20a_ecc_stat tex_unique_ded_pipe1_count; | 53 | struct gk20a_ecc_stat tex_unique_ded_pipe1_count; |
58 | 54 | ||
59 | #ifdef CONFIG_TEGRA_19x_GPU | 55 | struct gk20a_ecc_stat sm_l1_tag_corrected_err_count; |
60 | struct ecc_gr_t19x t19x; | 56 | struct gk20a_ecc_stat sm_l1_tag_uncorrected_err_count; |
61 | #endif | 57 | struct gk20a_ecc_stat sm_cbu_corrected_err_count; |
58 | struct gk20a_ecc_stat sm_cbu_uncorrected_err_count; | ||
59 | struct gk20a_ecc_stat sm_l1_data_corrected_err_count; | ||
60 | struct gk20a_ecc_stat sm_l1_data_uncorrected_err_count; | ||
61 | struct gk20a_ecc_stat sm_icache_corrected_err_count; | ||
62 | struct gk20a_ecc_stat sm_icache_uncorrected_err_count; | ||
63 | struct gk20a_ecc_stat gcc_l15_corrected_err_count; | ||
64 | struct gk20a_ecc_stat gcc_l15_uncorrected_err_count; | ||
65 | struct gk20a_ecc_stat fecs_corrected_err_count; | ||
66 | struct gk20a_ecc_stat fecs_uncorrected_err_count; | ||
67 | struct gk20a_ecc_stat gpccs_corrected_err_count; | ||
68 | struct gk20a_ecc_stat gpccs_uncorrected_err_count; | ||
69 | struct gk20a_ecc_stat mmu_l1tlb_corrected_err_count; | ||
70 | struct gk20a_ecc_stat mmu_l1tlb_uncorrected_err_count; | ||
62 | } gr; | 71 | } gr; |
63 | 72 | ||
64 | struct { | 73 | struct { |
65 | struct gk20a_ecc_stat l2_sec_count; | 74 | struct gk20a_ecc_stat l2_sec_count; |
66 | struct gk20a_ecc_stat l2_ded_count; | 75 | struct gk20a_ecc_stat l2_ded_count; |
67 | #ifdef CONFIG_TEGRA_19x_GPU | 76 | struct gk20a_ecc_stat l2_cache_corrected_err_count; |
68 | struct ecc_ltc_t19x t19x; | 77 | struct gk20a_ecc_stat l2_cache_uncorrected_err_count; |
69 | #endif | ||
70 | } ltc; | 78 | } ltc; |
71 | 79 | ||
72 | struct { | 80 | struct { |
73 | #ifdef CONFIG_TEGRA_19x_GPU | 81 | struct gk20a_ecc_stat mmu_l2tlb_corrected_err_count; |
74 | struct ecc_eng_t19x t19x; | 82 | struct gk20a_ecc_stat mmu_l2tlb_uncorrected_err_count; |
75 | #endif | 83 | struct gk20a_ecc_stat mmu_hubtlb_corrected_err_count; |
76 | } eng; | 84 | struct gk20a_ecc_stat mmu_hubtlb_uncorrected_err_count; |
85 | struct gk20a_ecc_stat mmu_fillunit_corrected_err_count; | ||
86 | struct gk20a_ecc_stat mmu_fillunit_uncorrected_err_count; | ||
87 | } fb; | ||
88 | |||
89 | struct { | ||
90 | struct gk20a_ecc_stat pmu_corrected_err_count; | ||
91 | struct gk20a_ecc_stat pmu_uncorrected_err_count; | ||
92 | } pmu; | ||
77 | 93 | ||
78 | }; | 94 | }; |
79 | 95 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index af0630d2..a925b1e2 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -1,9 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * drivers/video/tegra/host/gk20a/fifo_gk20a.h | ||
3 | * | ||
4 | * GK20A graphics fifo (gr host) | 2 | * GK20A graphics fifo (gr host) |
5 | * | 3 | * |
6 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
7 | * | 5 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
9 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -29,10 +27,6 @@ | |||
29 | #include "channel_gk20a.h" | 27 | #include "channel_gk20a.h" |
30 | #include "tsg_gk20a.h" | 28 | #include "tsg_gk20a.h" |
31 | 29 | ||
32 | #ifdef CONFIG_TEGRA_19x_GPU | ||
33 | #include "fifo_t19x.h" | ||
34 | #endif | ||
35 | |||
36 | #include <nvgpu/kref.h> | 30 | #include <nvgpu/kref.h> |
37 | 31 | ||
38 | struct gk20a_debug_output; | 32 | struct gk20a_debug_output; |
@@ -213,9 +207,7 @@ struct fifo_gk20a { | |||
213 | bool deferred_reset_pending; | 207 | bool deferred_reset_pending; |
214 | struct nvgpu_mutex deferred_reset_mutex; | 208 | struct nvgpu_mutex deferred_reset_mutex; |
215 | 209 | ||
216 | #ifdef CONFIG_TEGRA_19x_GPU | 210 | u32 max_subctx_count; |
217 | struct fifo_t19x t19x; | ||
218 | #endif | ||
219 | u32 channel_base; | 211 | u32 channel_base; |
220 | }; | 212 | }; |
221 | 213 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index c967b69b..b4886e31 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics | 2 | * GK20A Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -48,10 +48,6 @@ | |||
48 | #include "bus_gk20a.h" | 48 | #include "bus_gk20a.h" |
49 | #include "pstate/pstate.h" | 49 | #include "pstate/pstate.h" |
50 | 50 | ||
51 | #ifdef CONFIG_TEGRA_19x_GPU | ||
52 | #include "nvgpu_gpuid_t19x.h" | ||
53 | #endif | ||
54 | |||
55 | void __nvgpu_check_gpu_state(struct gk20a *g) | 51 | void __nvgpu_check_gpu_state(struct gk20a *g) |
56 | { | 52 | { |
57 | u32 boot_0 = 0xffffffff; | 53 | u32 boot_0 = 0xffffffff; |
@@ -127,7 +123,7 @@ int gk20a_prepare_poweroff(struct gk20a *g) | |||
127 | int gk20a_finalize_poweron(struct gk20a *g) | 123 | int gk20a_finalize_poweron(struct gk20a *g) |
128 | { | 124 | { |
129 | int err; | 125 | int err; |
130 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU) | 126 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) |
131 | u32 nr_pages; | 127 | u32 nr_pages; |
132 | #endif | 128 | #endif |
133 | 129 | ||
@@ -319,7 +315,7 @@ int gk20a_finalize_poweron(struct gk20a *g) | |||
319 | } | 315 | } |
320 | } | 316 | } |
321 | 317 | ||
322 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU) | 318 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) |
323 | if (gk20a_platform_has_syncpoints(g) && g->syncpt_unit_size) { | 319 | if (gk20a_platform_has_syncpoints(g) && g->syncpt_unit_size) { |
324 | if (!nvgpu_mem_is_valid(&g->syncpt_mem)) { | 320 | if (!nvgpu_mem_is_valid(&g->syncpt_mem)) { |
325 | nr_pages = DIV_ROUND_UP(g->syncpt_unit_size, PAGE_SIZE); | 321 | nr_pages = DIV_ROUND_UP(g->syncpt_unit_size, PAGE_SIZE); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 50f827a9..cc62865c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1342,7 +1342,7 @@ struct gk20a { | |||
1342 | 1342 | ||
1343 | u64 dma_memory_used; | 1343 | u64 dma_memory_used; |
1344 | 1344 | ||
1345 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) && defined(CONFIG_TEGRA_19x_GPU) | 1345 | #if defined(CONFIG_TEGRA_GK20A_NVHOST) |
1346 | u64 syncpt_unit_base; | 1346 | u64 syncpt_unit_base; |
1347 | size_t syncpt_unit_size; | 1347 | size_t syncpt_unit_size; |
1348 | u32 syncpt_size; | 1348 | u32 syncpt_size; |
@@ -1479,6 +1479,8 @@ int gk20a_wait_for_idle(struct gk20a *g); | |||
1479 | #define NVGPU_GPUID_GP10B 0x0000013B | 1479 | #define NVGPU_GPUID_GP10B 0x0000013B |
1480 | #define NVGPU_GPUID_GP104 0x00000134 | 1480 | #define NVGPU_GPUID_GP104 0x00000134 |
1481 | #define NVGPU_GPUID_GP106 0x00000136 | 1481 | #define NVGPU_GPUID_GP106 0x00000136 |
1482 | #define NVGPU_GPUID_GV11B 0x0000015B | ||
1483 | #define NVGPU_GPUID_GV100 0x00000140 | ||
1482 | 1484 | ||
1483 | int gk20a_init_gpu_characteristics(struct gk20a *g); | 1485 | int gk20a_init_gpu_characteristics(struct gk20a *g); |
1484 | 1486 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 6cc15c94..d1c32c03 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -24,10 +24,6 @@ | |||
24 | #ifndef GR_GK20A_H | 24 | #ifndef GR_GK20A_H |
25 | #define GR_GK20A_H | 25 | #define GR_GK20A_H |
26 | 26 | ||
27 | #ifdef CONFIG_TEGRA_19x_GPU | ||
28 | #include "gr_t19x.h" | ||
29 | #endif | ||
30 | |||
31 | #include "gr_ctx_gk20a.h" | 27 | #include "gr_ctx_gk20a.h" |
32 | #include "mm_gk20a.h" | 28 | #include "mm_gk20a.h" |
33 | 29 | ||
@@ -199,6 +195,12 @@ struct zbc_depth_table { | |||
199 | u32 ref_cnt; | 195 | u32 ref_cnt; |
200 | }; | 196 | }; |
201 | 197 | ||
198 | struct zbc_s_table { | ||
199 | u32 stencil; | ||
200 | u32 format; | ||
201 | u32 ref_cnt; | ||
202 | }; | ||
203 | |||
202 | struct zbc_entry { | 204 | struct zbc_entry { |
203 | u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; | 205 | u32 color_ds[GK20A_ZBC_COLOR_VALUE_SIZE]; |
204 | u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE]; | 206 | u32 color_l2[GK20A_ZBC_COLOR_VALUE_SIZE]; |
@@ -393,20 +395,14 @@ struct gr_gk20a { | |||
393 | struct nvgpu_mutex zbc_lock; | 395 | struct nvgpu_mutex zbc_lock; |
394 | struct zbc_color_table zbc_col_tbl[GK20A_ZBC_TABLE_SIZE]; | 396 | struct zbc_color_table zbc_col_tbl[GK20A_ZBC_TABLE_SIZE]; |
395 | struct zbc_depth_table zbc_dep_tbl[GK20A_ZBC_TABLE_SIZE]; | 397 | struct zbc_depth_table zbc_dep_tbl[GK20A_ZBC_TABLE_SIZE]; |
396 | #ifdef CONFIG_TEGRA_19x_GPU | ||
397 | struct zbc_s_table zbc_s_tbl[GK20A_ZBC_TABLE_SIZE]; | 398 | struct zbc_s_table zbc_s_tbl[GK20A_ZBC_TABLE_SIZE]; |
398 | #endif | ||
399 | s32 max_default_color_index; | 399 | s32 max_default_color_index; |
400 | s32 max_default_depth_index; | 400 | s32 max_default_depth_index; |
401 | #ifdef CONFIG_TEGRA_19x_GPU | ||
402 | s32 max_default_s_index; | 401 | s32 max_default_s_index; |
403 | #endif | ||
404 | 402 | ||
405 | u32 max_used_color_index; | 403 | u32 max_used_color_index; |
406 | u32 max_used_depth_index; | 404 | u32 max_used_depth_index; |
407 | #ifdef CONFIG_TEGRA_19x_GPU | ||
408 | u32 max_used_s_index; | 405 | u32 max_used_s_index; |
409 | #endif | ||
410 | 406 | ||
411 | #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ | 407 | #define GR_CHANNEL_MAP_TLB_SIZE 2 /* must of power of 2 */ |
412 | struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; | 408 | struct gr_channel_map_tlb_entry chid_tlb[GR_CHANNEL_MAP_TLB_SIZE]; |
diff --git a/drivers/gpu/nvgpu/gk20a/hal.c b/drivers/gpu/nvgpu/gk20a/hal.c index d24d4bc5..ec6816c6 100644 --- a/drivers/gpu/nvgpu/gk20a/hal.c +++ b/drivers/gpu/nvgpu/gk20a/hal.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * NVIDIA GPU HAL interface. | 2 | * NVIDIA GPU HAL interface. |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -27,10 +27,8 @@ | |||
27 | #include "gm20b/hal_gm20b.h" | 27 | #include "gm20b/hal_gm20b.h" |
28 | #include "gp10b/hal_gp10b.h" | 28 | #include "gp10b/hal_gp10b.h" |
29 | #include "gp106/hal_gp106.h" | 29 | #include "gp106/hal_gp106.h" |
30 | 30 | #include "gv100/hal_gv100.h" | |
31 | #ifdef CONFIG_TEGRA_19x_GPU | 31 | #include "gv11b/hal_gv11b.h" |
32 | #include "nvgpu_gpuid_t19x.h" | ||
33 | #endif | ||
34 | 32 | ||
35 | #include <nvgpu/log.h> | 33 | #include <nvgpu/log.h> |
36 | 34 | ||
@@ -53,17 +51,15 @@ int gpu_init_hal(struct gk20a *g) | |||
53 | if (gp106_init_hal(g)) | 51 | if (gp106_init_hal(g)) |
54 | return -ENODEV; | 52 | return -ENODEV; |
55 | break; | 53 | break; |
56 | #ifdef CONFIG_TEGRA_19x_GPU | 54 | case NVGPU_GPUID_GV11B: |
57 | case TEGRA_19x_GPUID: | 55 | if (gv11b_init_hal(g)) |
58 | if (TEGRA_19x_GPUID_HAL(g)) | ||
59 | return -ENODEV; | 56 | return -ENODEV; |
60 | break; | 57 | break; |
61 | case BIGGPU_19x_GPUID: | 58 | case NVGPU_GPUID_GV100: |
62 | if (BIGGPU_19x_GPUID_HAL(g)) | 59 | if (gv100_init_hal(g)) |
63 | return -ENODEV; | 60 | return -ENODEV; |
64 | break; | 61 | break; |
65 | 62 | ||
66 | #endif | ||
67 | default: | 63 | default: |
68 | nvgpu_err(g, "no support for %x", ver); | 64 | nvgpu_err(g, "no support for %x", ver); |
69 | return -ENODEV; | 65 | return -ENODEV; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 9c2f72fb..603d25fe 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A PMU (aka. gPMU outside gk20a context) | 2 | * GK20A PMU (aka. gPMU outside gk20a context) |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -39,10 +39,6 @@ | |||
39 | #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> | 39 | #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> |
40 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> | 40 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> |
41 | 41 | ||
42 | #ifdef CONFIG_TEGRA_19x_GPU | ||
43 | #include "nvgpu_gpuid_t19x.h" | ||
44 | #endif | ||
45 | |||
46 | #define gk20a_dbg_pmu(fmt, arg...) \ | 42 | #define gk20a_dbg_pmu(fmt, arg...) \ |
47 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | 43 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) |
48 | 44 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h index 2168cb4f..438002e4 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -28,9 +28,6 @@ | |||
28 | 28 | ||
29 | #include "gr_gk20a.h" | 29 | #include "gr_gk20a.h" |
30 | 30 | ||
31 | #ifdef CONFIG_TEGRA_19x_GPU | ||
32 | #include "tsg_t19x.h" | ||
33 | #endif | ||
34 | #define NVGPU_INVALID_TSG_ID (-1) | 31 | #define NVGPU_INVALID_TSG_ID (-1) |
35 | 32 | ||
36 | struct channel_gk20a; | 33 | struct channel_gk20a; |
@@ -68,9 +65,9 @@ struct tsg_gk20a { | |||
68 | u32 runlist_id; | 65 | u32 runlist_id; |
69 | pid_t tgid; | 66 | pid_t tgid; |
70 | struct nvgpu_mem *eng_method_buffers; | 67 | struct nvgpu_mem *eng_method_buffers; |
71 | #ifdef CONFIG_TEGRA_19x_GPU | 68 | u32 num_active_tpcs; |
72 | struct tsg_t19x t19x; | 69 | u8 tpc_pg_enabled; |
73 | #endif | 70 | bool tpc_num_initialized; |
74 | 71 | ||
75 | struct nvgpu_gr_ctx gr_ctx; | 72 | struct nvgpu_gr_ctx gr_ctx; |
76 | }; | 73 | }; |