diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 37 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 52 |
2 files changed, 89 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0cb6c933..63dfc12d 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -2801,6 +2801,42 @@ int gk20a_alloc_obj_ctx(struct channel_gk20a *c, | |||
2801 | gr_gk20a_commit_global_ctx_buffers(g, c, true)); | 2801 | gr_gk20a_commit_global_ctx_buffers(g, c, true)); |
2802 | } | 2802 | } |
2803 | 2803 | ||
2804 | /* tweak any perf parameters per-context here */ | ||
2805 | if (args->class_num == KEPLER_COMPUTE_A) { | ||
2806 | int begin_err; | ||
2807 | u32 tex_lock_disable_mask = | ||
2808 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_m() | | ||
2809 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_m() | | ||
2810 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_m() | | ||
2811 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_m() | | ||
2812 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_m() | | ||
2813 | gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_m(); | ||
2814 | |||
2815 | u32 texlock = gk20a_readl(g, gr_gpcs_tpcs_sm_sch_texlock_r()); | ||
2816 | |||
2817 | texlock = (texlock & ~tex_lock_disable_mask) | | ||
2818 | (gr_gpcs_tpcs_sm_sch_texlock_tex_hash_disable_f() | | ||
2819 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_disable_f() | | ||
2820 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_disable_f() | | ||
2821 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_disable_f() | | ||
2822 | gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_disable_f() | | ||
2823 | gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_disable_f()); | ||
2824 | |||
2825 | begin_err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); | ||
2826 | |||
2827 | if (!begin_err) { | ||
2828 | err = gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
2829 | gr_gpcs_tpcs_sm_sch_texlock_r(), | ||
2830 | texlock, true); | ||
2831 | } | ||
2832 | if ((begin_err || err)) { | ||
2833 | gk20a_err(dev_from_gk20a(g), | ||
2834 | "failed to set texlock for compute class"); | ||
2835 | } | ||
2836 | if (!begin_err) | ||
2837 | gr_gk20a_ctx_patch_write_end(g, ch_ctx); | ||
2838 | } | ||
2839 | |||
2804 | /* init golden image, ELPG enabled after this is done */ | 2840 | /* init golden image, ELPG enabled after this is done */ |
2805 | err = gr_gk20a_init_golden_ctx_image(g, c); | 2841 | err = gr_gk20a_init_golden_ctx_image(g, c); |
2806 | if (err) { | 2842 | if (err) { |
@@ -4072,6 +4108,7 @@ static void gk20a_gr_enable_gpc_exceptions(struct gk20a *g) | |||
4072 | gr_gpc0_gpccs_gpc_exception_en_tpc_0_enabled_f()); | 4108 | gr_gpc0_gpccs_gpc_exception_en_tpc_0_enabled_f()); |
4073 | } | 4109 | } |
4074 | 4110 | ||
4111 | |||
4075 | void gr_gk20a_enable_hww_exceptions(struct gk20a *g) | 4112 | void gr_gk20a_enable_hww_exceptions(struct gk20a *g) |
4076 | { | 4113 | { |
4077 | /* enable exceptions */ | 4114 | /* enable exceptions */ |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index a28a1d0d..fad8d3a6 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -3190,4 +3190,56 @@ static inline u32 gr_gpc0_tpc0_l1c_dbg_cya15_en_f(void) | |||
3190 | { | 3190 | { |
3191 | return 0x8000000; | 3191 | return 0x8000000; |
3192 | } | 3192 | } |
3193 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_r(void) | ||
3194 | { | ||
3195 | return 0x00419ec8; | ||
3196 | } | ||
3197 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_m(void) | ||
3198 | { | ||
3199 | return 0x1 << 0; | ||
3200 | } | ||
3201 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_disable_f(void) | ||
3202 | { | ||
3203 | return 0x0; | ||
3204 | } | ||
3205 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_m(void) | ||
3206 | { | ||
3207 | return 0x1 << 1; | ||
3208 | } | ||
3209 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tile_disable_f(void) | ||
3210 | { | ||
3211 | return 0x0; | ||
3212 | } | ||
3213 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_m(void) | ||
3214 | { | ||
3215 | return 0x1 << 2; | ||
3216 | } | ||
3217 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_phase_disable_f(void) | ||
3218 | { | ||
3219 | return 0x0; | ||
3220 | } | ||
3221 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_m(void) | ||
3222 | { | ||
3223 | return 0x1 << 3; | ||
3224 | } | ||
3225 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_tex_disable_f(void) | ||
3226 | { | ||
3227 | return 0x0; | ||
3228 | } | ||
3229 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_m(void) | ||
3230 | { | ||
3231 | return 0xff << 4; | ||
3232 | } | ||
3233 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_tex_hash_timeout_disable_f(void) | ||
3234 | { | ||
3235 | return 0x0; | ||
3236 | } | ||
3237 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_m(void) | ||
3238 | { | ||
3239 | return 0x1 << 16; | ||
3240 | } | ||
3241 | static inline u32 gr_gpcs_tpcs_sm_sch_texlock_dot_t_unlock_disable_f(void) | ||
3242 | { | ||
3243 | return 0x0; | ||
3244 | } | ||
3193 | #endif | 3245 | #endif |