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-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.c2
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h3
-rw-r--r--drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c119
-rw-r--r--drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h33
4 files changed, 3 insertions, 154 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 7fec4da7..24cfc6ec 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -187,7 +187,7 @@ int gk20a_finalize_poweron(struct gk20a *g)
187 if (g->ops.clk.disable_slowboot) 187 if (g->ops.clk.disable_slowboot)
188 g->ops.clk.disable_slowboot(g); 188 g->ops.clk.disable_slowboot(g);
189 189
190 gk20a_enable_priv_ring(g); 190 g->ops.priv_ring.enable_priv_ring(g);
191 191
192 /* TBD: move this after graphics init in which blcg/slcg is enabled. 192 /* TBD: move this after graphics init in which blcg/slcg is enabled.
193 This function removes SlowdownOnBoot which applies 32x divider 193 This function removes SlowdownOnBoot which applies 32x divider
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index bd477208..c29c03f0 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -69,7 +69,6 @@ struct nvgpu_ctxsw_trace_filter;
69#include "fifo_gk20a.h" 69#include "fifo_gk20a.h"
70#include "tsg_gk20a.h" 70#include "tsg_gk20a.h"
71#include "pmu_gk20a.h" 71#include "pmu_gk20a.h"
72#include "priv_ring_gk20a.h"
73#include "therm_gk20a.h" 72#include "therm_gk20a.h"
74#include "clk/clk.h" 73#include "clk/clk.h"
75#include "perf/perf.h" 74#include "perf/perf.h"
@@ -1235,9 +1234,11 @@ struct gpu_ops {
1235 void (*falcon_hal_sw_init)(struct nvgpu_falcon *flcn); 1234 void (*falcon_hal_sw_init)(struct nvgpu_falcon *flcn);
1236 } falcon; 1235 } falcon;
1237 struct { 1236 struct {
1237 void (*enable_priv_ring)(struct gk20a *g);
1238 void (*isr)(struct gk20a *g); 1238 void (*isr)(struct gk20a *g);
1239 void (*decode_error_code)(struct gk20a *g, u32 error_code); 1239 void (*decode_error_code)(struct gk20a *g, u32 error_code);
1240 void (*set_ppriv_timeout_settings)(struct gk20a *g); 1240 void (*set_ppriv_timeout_settings)(struct gk20a *g);
1241 u32 (*enum_ltc)(struct gk20a *g);
1241 } priv_ring; 1242 } priv_ring;
1242 struct { 1243 struct {
1243 int (*check_priv_security)(struct gk20a *g); 1244 int (*check_priv_security)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
deleted file mode 100644
index 0e004a5d..00000000
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
+++ /dev/null
@@ -1,119 +0,0 @@
1/*
2 * GK20A priv ring
3 *
4 * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#include "gk20a.h"
26
27#include <nvgpu/log.h>
28#include <nvgpu/timers.h>
29#include <nvgpu/enabled.h>
30#include <nvgpu/io.h>
31#include <nvgpu/utils.h>
32
33#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
34#include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h>
35#include <nvgpu/hw/gk20a/hw_pri_ringstation_sys_gk20a.h>
36#include <nvgpu/hw/gk20a/hw_pri_ringstation_gpc_gk20a.h>
37#include <nvgpu/hw/gk20a/hw_pri_ringstation_fbp_gk20a.h>
38
39void gk20a_enable_priv_ring(struct gk20a *g)
40{
41 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
42 return;
43
44 nvgpu_log(g, gpu_dbg_info, "enabling priv ring");
45
46 if (g->ops.clock_gating.slcg_priring_load_gating_prod)
47 g->ops.clock_gating.slcg_priring_load_gating_prod(g,
48 g->slcg_enabled);
49
50 gk20a_writel(g,pri_ringmaster_command_r(),
51 0x4);
52
53 gk20a_writel(g, pri_ringstation_sys_decode_config_r(),
54 0x2);
55 gk20a_readl(g, pri_ringstation_sys_decode_config_r());
56}
57
58void gk20a_priv_ring_isr(struct gk20a *g)
59{
60 u32 status0, status1;
61 u32 cmd;
62 s32 retry = 100;
63 u32 gpc;
64 u32 gpc_priv_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_PRIV_STRIDE);
65
66 if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
67 return;
68
69 status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r());
70 status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r());
71
72 nvgpu_log(g, gpu_dbg_intr, "ringmaster intr status0: 0x%08x,"
73 "status1: 0x%08x", status0, status1);
74
75 if (pri_ringmaster_intr_status0_gbl_write_error_sys_v(status0) != 0) {
76 nvgpu_log(g, gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x",
77 gk20a_readl(g, pri_ringstation_sys_priv_error_adr_r()),
78 gk20a_readl(g, pri_ringstation_sys_priv_error_wrdat_r()),
79 gk20a_readl(g, pri_ringstation_sys_priv_error_info_r()),
80 gk20a_readl(g, pri_ringstation_sys_priv_error_code_r()));
81 }
82
83 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
84 if (status1 & BIT(gpc)) {
85 nvgpu_log(g, gpu_dbg_intr, "GPC%u write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", gpc,
86 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_adr_r() + gpc * gpc_priv_stride),
87 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_wrdat_r() + gpc * gpc_priv_stride),
88 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_info_r() + gpc * gpc_priv_stride),
89 gk20a_readl(g, pri_ringstation_gpc_gpc0_priv_error_code_r() + gpc * gpc_priv_stride));
90 }
91 }
92 /* clear interrupt */
93 cmd = gk20a_readl(g, pri_ringmaster_command_r());
94 cmd = set_field(cmd, pri_ringmaster_command_cmd_m(),
95 pri_ringmaster_command_cmd_ack_interrupt_f());
96 gk20a_writel(g, pri_ringmaster_command_r(), cmd);
97 /* poll for clear interrupt done */
98 cmd = pri_ringmaster_command_cmd_v(
99 gk20a_readl(g, pri_ringmaster_command_r()));
100 while (cmd != pri_ringmaster_command_cmd_no_cmd_v() && retry) {
101 nvgpu_udelay(20);
102 retry--;
103 cmd = pri_ringmaster_command_cmd_v(
104 gk20a_readl(g, pri_ringmaster_command_r()));
105 }
106 if (retry == 0 && cmd != pri_ringmaster_command_cmd_no_cmd_v())
107 nvgpu_warn(g, "priv ringmaster intr ack too many retries");
108}
109
110void gk20a_priv_set_timeout_settings(struct gk20a *g)
111{
112 /*
113 * Bug 1340570: increase the clock timeout to avoid potential
114 * operation failure at high gpcclk rate. Default values are 0x400.
115 */
116 nvgpu_writel(g, pri_ringstation_sys_master_config_r(0x15), 0x800);
117 nvgpu_writel(g, pri_ringstation_gpc_master_config_r(0xa), 0x800);
118 nvgpu_writel(g, pri_ringstation_fbp_master_config_r(0x8), 0x800);
119}
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h
deleted file mode 100644
index 98040624..00000000
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*
2 * GK20A PRIV ringmaster
3 *
4 * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24#ifndef __PRIV_RING_GK20A_H__
25#define __PRIV_RING_GK20A_H__
26
27struct gpu_ops;
28
29void gk20a_priv_ring_isr(struct gk20a *g);
30void gk20a_enable_priv_ring(struct gk20a *g);
31void gk20a_priv_set_timeout_settings(struct gk20a *g);
32
33#endif /*__PRIV_RING_GK20A_H__*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-16 18:34:09 -0400