diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mm_gk20a.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 16 |
7 files changed, 16 insertions, 21 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index 436d3205..6df8f6e4 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -39,7 +39,6 @@ | |||
39 | #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h> | 39 | #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h> |
40 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> | 40 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> |
41 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> | 41 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> |
42 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
43 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | 42 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> |
44 | #include <nvgpu/barrier.h> | 43 | #include <nvgpu/barrier.h> |
45 | 44 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c index 00d1b196..28a3d495 100644 --- a/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/css_gr_gk20a.c | |||
@@ -34,12 +34,12 @@ | |||
34 | #include <nvgpu/io.h> | 34 | #include <nvgpu/io.h> |
35 | #include <nvgpu/utils.h> | 35 | #include <nvgpu/utils.h> |
36 | #include <nvgpu/channel.h> | 36 | #include <nvgpu/channel.h> |
37 | #include <nvgpu/unit.h> | ||
37 | 38 | ||
38 | #include "gk20a.h" | 39 | #include "gk20a.h" |
39 | #include "css_gr_gk20a.h" | 40 | #include "css_gr_gk20a.h" |
40 | 41 | ||
41 | #include <nvgpu/hw/gk20a/hw_perf_gk20a.h> | 42 | #include <nvgpu/hw/gk20a/hw_perf_gk20a.h> |
42 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
43 | 43 | ||
44 | /* check client for pointed perfmon ownership */ | 44 | /* check client for pointed perfmon ownership */ |
45 | #define CONTAINS_PERFMON(cl, pm) \ | 45 | #define CONTAINS_PERFMON(cl, pm) \ |
@@ -89,7 +89,7 @@ static void css_hw_reset_streaming(struct gk20a *g) | |||
89 | u32 engine_status; | 89 | u32 engine_status; |
90 | 90 | ||
91 | /* reset the perfmon */ | 91 | /* reset the perfmon */ |
92 | g->ops.mc.reset(g, mc_enable_perfmon_enabled_f()); | 92 | g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON)); |
93 | 93 | ||
94 | /* RBUFEMPTY must be set -- otherwise we'll pick up */ | 94 | /* RBUFEMPTY must be set -- otherwise we'll pick up */ |
95 | /* snapshot that have been queued up from earlier */ | 95 | /* snapshot that have been queued up from earlier */ |
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index ef505425..adc13c3d 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include <nvgpu/io.h> | 31 | #include <nvgpu/io.h> |
32 | #include <nvgpu/utils.h> | 32 | #include <nvgpu/utils.h> |
33 | #include <nvgpu/channel.h> | 33 | #include <nvgpu/channel.h> |
34 | #include <nvgpu/unit.h> | ||
34 | 35 | ||
35 | #include "gk20a.h" | 36 | #include "gk20a.h" |
36 | #include "gr_gk20a.h" | 37 | #include "gr_gk20a.h" |
@@ -39,14 +40,13 @@ | |||
39 | 40 | ||
40 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | 41 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> |
41 | #include <nvgpu/hw/gk20a/hw_perf_gk20a.h> | 42 | #include <nvgpu/hw/gk20a/hw_perf_gk20a.h> |
42 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
43 | 43 | ||
44 | static void gk20a_perfbuf_reset_streaming(struct gk20a *g) | 44 | static void gk20a_perfbuf_reset_streaming(struct gk20a *g) |
45 | { | 45 | { |
46 | u32 engine_status; | 46 | u32 engine_status; |
47 | u32 num_unread_bytes; | 47 | u32 num_unread_bytes; |
48 | 48 | ||
49 | g->ops.mc.reset(g, mc_enable_perfmon_enabled_f()); | 49 | g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON)); |
50 | 50 | ||
51 | engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r()); | 51 | engine_status = gk20a_readl(g, perf_pmasys_enginestatus_r()); |
52 | WARN_ON(0u == | 52 | WARN_ON(0u == |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index e1702bd7..3632963a 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -44,6 +44,7 @@ | |||
44 | #include <nvgpu/io.h> | 44 | #include <nvgpu/io.h> |
45 | #include <nvgpu/utils.h> | 45 | #include <nvgpu/utils.h> |
46 | #include <nvgpu/channel.h> | 46 | #include <nvgpu/channel.h> |
47 | #include <nvgpu/unit.h> | ||
47 | 48 | ||
48 | #include "gk20a.h" | 49 | #include "gk20a.h" |
49 | #include "mm_gk20a.h" | 50 | #include "mm_gk20a.h" |
@@ -53,7 +54,6 @@ | |||
53 | #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h> | 54 | #include <nvgpu/hw/gk20a/hw_ccsr_gk20a.h> |
54 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> | 55 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> |
55 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> | 56 | #include <nvgpu/hw/gk20a/hw_top_gk20a.h> |
56 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
57 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> | 57 | #include <nvgpu/hw/gk20a/hw_gr_gk20a.h> |
58 | 58 | ||
59 | #define FECS_METHOD_WFI_RESTORE 0x80000 | 59 | #define FECS_METHOD_WFI_RESTORE 0x80000 |
@@ -822,7 +822,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
822 | nvgpu_log_fn(g, " "); | 822 | nvgpu_log_fn(g, " "); |
823 | 823 | ||
824 | /* enable pmc pfifo */ | 824 | /* enable pmc pfifo */ |
825 | g->ops.mc.reset(g, mc_enable_pfifo_enabled_f()); | 825 | g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_FIFO)); |
826 | 826 | ||
827 | if (g->ops.clock_gating.slcg_fifo_load_gating_prod) { | 827 | if (g->ops.clock_gating.slcg_fifo_load_gating_prod) { |
828 | g->ops.clock_gating.slcg_fifo_load_gating_prod(g, | 828 | g->ops.clock_gating.slcg_fifo_load_gating_prod(g, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0250e97e..6e63c138 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -42,6 +42,7 @@ | |||
42 | #include <nvgpu/io.h> | 42 | #include <nvgpu/io.h> |
43 | #include <nvgpu/utils.h> | 43 | #include <nvgpu/utils.h> |
44 | #include <nvgpu/channel.h> | 44 | #include <nvgpu/channel.h> |
45 | #include <nvgpu/unit.h> | ||
45 | 46 | ||
46 | #include "gk20a.h" | 47 | #include "gk20a.h" |
47 | #include "gr_gk20a.h" | 48 | #include "gr_gk20a.h" |
@@ -4708,9 +4709,9 @@ static int gk20a_init_gr_prepare(struct gk20a *g) | |||
4708 | u32 err = 0; | 4709 | u32 err = 0; |
4709 | 4710 | ||
4710 | /* reset gr engine */ | 4711 | /* reset gr engine */ |
4711 | g->ops.mc.reset(g, mc_enable_pgraph_enabled_f() | | 4712 | g->ops.mc.reset(g, g->ops.mc.reset_mask(g, NVGPU_UNIT_GRAPH) | |
4712 | mc_enable_blg_enabled_f() | | 4713 | g->ops.mc.reset_mask(g, NVGPU_UNIT_BLG) | |
4713 | mc_enable_perfmon_enabled_f()); | 4714 | g->ops.mc.reset_mask(g, NVGPU_UNIT_PERFMON)); |
4714 | 4715 | ||
4715 | gr_gk20a_load_gating_prod(g); | 4716 | gr_gk20a_load_gating_prod(g); |
4716 | 4717 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c index 6d5bea30..2e57d01e 100644 --- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c | |||
@@ -51,7 +51,6 @@ | |||
51 | #include <nvgpu/hw/gk20a/hw_gmmu_gk20a.h> | 51 | #include <nvgpu/hw/gk20a/hw_gmmu_gk20a.h> |
52 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> | 52 | #include <nvgpu/hw/gk20a/hw_ram_gk20a.h> |
53 | #include <nvgpu/hw/gk20a/hw_pram_gk20a.h> | 53 | #include <nvgpu/hw/gk20a/hw_pram_gk20a.h> |
54 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | ||
55 | #include <nvgpu/hw/gk20a/hw_flush_gk20a.h> | 54 | #include <nvgpu/hw/gk20a/hw_flush_gk20a.h> |
56 | 55 | ||
57 | /* | 56 | /* |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index f231e088..6eecc4fa 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -34,6 +34,7 @@ | |||
34 | #include <nvgpu/io.h> | 34 | #include <nvgpu/io.h> |
35 | #include <nvgpu/clk_arb.h> | 35 | #include <nvgpu/clk_arb.h> |
36 | #include <nvgpu/utils.h> | 36 | #include <nvgpu/utils.h> |
37 | #include <nvgpu/unit.h> | ||
37 | 38 | ||
38 | #include "gk20a.h" | 39 | #include "gk20a.h" |
39 | #include "gr_gk20a.h" | 40 | #include "gr_gk20a.h" |
@@ -497,24 +498,21 @@ void gk20a_write_dmatrfbase(struct gk20a *g, u32 addr) | |||
497 | 498 | ||
498 | bool gk20a_pmu_is_engine_in_reset(struct gk20a *g) | 499 | bool gk20a_pmu_is_engine_in_reset(struct gk20a *g) |
499 | { | 500 | { |
500 | u32 pmc_enable; | ||
501 | bool status = false; | 501 | bool status = false; |
502 | 502 | ||
503 | pmc_enable = gk20a_readl(g, mc_enable_r()); | 503 | status = g->ops.mc.is_enabled(g, NVGPU_UNIT_PWR); |
504 | if (mc_enable_pwr_v(pmc_enable) == | ||
505 | mc_enable_pwr_disabled_v()) { | ||
506 | status = true; | ||
507 | } | ||
508 | 504 | ||
509 | return status; | 505 | return status; |
510 | } | 506 | } |
511 | 507 | ||
512 | int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset) | 508 | int gk20a_pmu_engine_reset(struct gk20a *g, bool do_reset) |
513 | { | 509 | { |
510 | u32 reset_mask = g->ops.mc.reset_mask(g, NVGPU_UNIT_PWR); | ||
511 | |||
514 | if (do_reset) { | 512 | if (do_reset) { |
515 | g->ops.mc.enable(g, mc_enable_pwr_enabled_f()); | 513 | g->ops.mc.enable(g, reset_mask); |
516 | } else { | 514 | } else { |
517 | g->ops.mc.disable(g, mc_enable_pwr_enabled_f()); | 515 | g->ops.mc.disable(g, reset_mask); |
518 | } | 516 | } |
519 | 517 | ||
520 | return 0; | 518 | return 0; |
@@ -659,8 +657,6 @@ void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu) | |||
659 | pwr_falcon_exterrstat_valid_true_v()) { | 657 | pwr_falcon_exterrstat_valid_true_v()) { |
660 | nvgpu_err(g, "pwr_falcon_exterraddr_r : 0x%x", | 658 | nvgpu_err(g, "pwr_falcon_exterraddr_r : 0x%x", |
661 | gk20a_readl(g, pwr_falcon_exterraddr_r())); | 659 | gk20a_readl(g, pwr_falcon_exterraddr_r())); |
662 | nvgpu_err(g, "pmc_enable : 0x%x", | ||
663 | gk20a_readl(g, mc_enable_r())); | ||
664 | } | 660 | } |
665 | 661 | ||
666 | /* Print PMU F/W debug prints */ | 662 | /* Print PMU F/W debug prints */ |