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Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.c26
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h14
-rw-r--r--drivers/gpu/nvgpu/gk20a/mc_gk20a.c5
3 files changed, 0 insertions, 45 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 21e861fe..6350bcf5 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -358,32 +358,6 @@ int gk20a_can_busy(struct gk20a *g)
358 return 1; 358 return 1;
359} 359}
360 360
361/*
362 * Start the process for unloading the driver. Set NVGPU_DRIVER_IS_DYING.
363 */
364void gk20a_driver_start_unload(struct gk20a *g)
365{
366 gk20a_dbg(gpu_dbg_shutdown, "Driver is now going down!\n");
367
368 down_write(&g->busy_lock);
369 __nvgpu_set_enabled(g, NVGPU_DRIVER_IS_DYING, true);
370 up_write(&g->busy_lock);
371
372 if (g->is_virtual)
373 return;
374
375 gk20a_wait_for_idle(dev_from_gk20a(g));
376
377 nvgpu_wait_for_deferred_interrupts(g);
378 gk20a_channel_cancel_pending_sema_waits(g);
379
380 if (g->nonstall_work_queue) {
381 cancel_work_sync(&g->nonstall_fn_work);
382 destroy_workqueue(g->nonstall_work_queue);
383 g->nonstall_work_queue = NULL;
384 }
385}
386
387int gk20a_wait_for_idle(struct device *dev) 361int gk20a_wait_for_idle(struct device *dev)
388{ 362{
389 struct gk20a *g = get_gk20a(dev); 363 struct gk20a *g = get_gk20a(dev);
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 90c35a7b..8d9318b2 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1042,10 +1042,6 @@ struct gk20a {
1042 1042
1043 atomic_t usage_count; 1043 atomic_t usage_count;
1044 1044
1045 atomic_t nonstall_ops;
1046 struct work_struct nonstall_fn_work;
1047 struct workqueue_struct *nonstall_work_queue;
1048
1049 struct kref refcount; 1045 struct kref refcount;
1050 1046
1051 struct resource *reg_mem; 1047 struct resource *reg_mem;
@@ -1224,15 +1220,6 @@ struct gk20a {
1224 u32 max_ltc_count; 1220 u32 max_ltc_count;
1225 u32 ltc_count; 1221 u32 ltc_count;
1226 1222
1227 atomic_t hw_irq_stall_count;
1228 atomic_t hw_irq_nonstall_count;
1229
1230 atomic_t sw_irq_stall_last_handled;
1231 wait_queue_head_t sw_irq_stall_last_handled_wq;
1232
1233 atomic_t sw_irq_nonstall_last_handled;
1234 wait_queue_head_t sw_irq_nonstall_last_handled_wq;
1235
1236 struct gk20a_channel_worker { 1223 struct gk20a_channel_worker {
1237 struct nvgpu_thread poll_task; 1224 struct nvgpu_thread poll_task;
1238 atomic_t put; 1225 atomic_t put;
@@ -1485,7 +1472,6 @@ int __gk20a_do_idle(struct gk20a *g, bool force_reset);
1485int __gk20a_do_unidle(struct gk20a *g); 1472int __gk20a_do_unidle(struct gk20a *g);
1486 1473
1487int gk20a_can_busy(struct gk20a *g); 1474int gk20a_can_busy(struct gk20a *g);
1488void gk20a_driver_start_unload(struct gk20a *g);
1489int gk20a_wait_for_idle(struct device *dev); 1475int gk20a_wait_for_idle(struct device *dev);
1490 1476
1491#define NVGPU_GPU_ARCHITECTURE_SHIFT 4 1477#define NVGPU_GPU_ARCHITECTURE_SHIFT 4
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index accda972..e25fcfc3 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -27,13 +27,11 @@
27void mc_gk20a_isr_stall(struct gk20a *g) 27void mc_gk20a_isr_stall(struct gk20a *g)
28{ 28{
29 u32 mc_intr_0; 29 u32 mc_intr_0;
30 int hw_irq_count;
31 u32 engine_id_idx; 30 u32 engine_id_idx;
32 u32 active_engine_id = 0; 31 u32 active_engine_id = 0;
33 u32 engine_enum = ENGINE_INVAL_GK20A; 32 u32 engine_enum = ENGINE_INVAL_GK20A;
34 33
35 mc_intr_0 = g->ops.mc.intr_stall(g); 34 mc_intr_0 = g->ops.mc.intr_stall(g);
36 hw_irq_count = atomic_read(&g->hw_irq_stall_count);
37 35
38 gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); 36 gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0);
39 37
@@ -67,9 +65,6 @@ void mc_gk20a_isr_stall(struct gk20a *g)
67 g->ops.ltc.isr(g); 65 g->ops.ltc.isr(g);
68 if (mc_intr_0 & mc_intr_0_pbus_pending_f()) 66 if (mc_intr_0 & mc_intr_0_pbus_pending_f())
69 g->ops.bus.isr(g); 67 g->ops.bus.isr(g);
70
71 /* sync handled irq counter before re-enabling interrupts */
72 atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count);
73} 68}
74 69
75void mc_gk20a_intr_enable(struct gk20a *g) 70void mc_gk20a_intr_enable(struct gk20a *g)