diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 13 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 4 |
2 files changed, 11 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index f12c78f8..f4b96b7a 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -2154,11 +2154,15 @@ int gk20a_fifo_tsg_unbind_channel_verify_status(struct channel_gk20a *ch) | |||
2154 | int gk20a_fifo_tsg_unbind_channel(struct channel_gk20a *ch) | 2154 | int gk20a_fifo_tsg_unbind_channel(struct channel_gk20a *ch) |
2155 | { | 2155 | { |
2156 | struct gk20a *g = ch->g; | 2156 | struct gk20a *g = ch->g; |
2157 | struct fifo_gk20a *f = &g->fifo; | 2157 | struct tsg_gk20a *tsg = tsg_gk20a_from_ch(ch); |
2158 | struct tsg_gk20a *tsg = &f->tsg[ch->tsgid]; | ||
2159 | int err; | 2158 | int err; |
2160 | bool tsg_timedout = false; | 2159 | bool tsg_timedout = false; |
2161 | 2160 | ||
2161 | if (tsg == NULL) { | ||
2162 | nvgpu_err(g, "chid: %d is not bound to tsg", ch->chid); | ||
2163 | return 0; | ||
2164 | } | ||
2165 | |||
2162 | /* If one channel in TSG times out, we disable all channels */ | 2166 | /* If one channel in TSG times out, we disable all channels */ |
2163 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); | 2167 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); |
2164 | tsg_timedout = gk20a_channel_check_timedout(ch); | 2168 | tsg_timedout = gk20a_channel_check_timedout(ch); |
@@ -2188,6 +2192,7 @@ int gk20a_fifo_tsg_unbind_channel(struct channel_gk20a *ch) | |||
2188 | /* Remove channel from TSG and re-enable rest of the channels */ | 2192 | /* Remove channel from TSG and re-enable rest of the channels */ |
2189 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); | 2193 | nvgpu_rwsem_down_write(&tsg->ch_list_lock); |
2190 | nvgpu_list_del(&ch->ch_entry); | 2194 | nvgpu_list_del(&ch->ch_entry); |
2195 | ch->tsgid = NVGPU_INVALID_TSG_ID; | ||
2191 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); | 2196 | nvgpu_rwsem_up_write(&tsg->ch_list_lock); |
2192 | 2197 | ||
2193 | /* | 2198 | /* |
@@ -3485,9 +3490,7 @@ int gk20a_fifo_update_runlist_locked(struct gk20a *g, u32 runlist_id, | |||
3485 | Otherwise, keep active list untouched for suspend/resume. */ | 3490 | Otherwise, keep active list untouched for suspend/resume. */ |
3486 | if (chid != FIFO_INVAL_CHANNEL_ID) { | 3491 | if (chid != FIFO_INVAL_CHANNEL_ID) { |
3487 | ch = &f->channel[chid]; | 3492 | ch = &f->channel[chid]; |
3488 | if (gk20a_is_channel_marked_as_tsg(ch)) { | 3493 | tsg = tsg_gk20a_from_ch(ch); |
3489 | tsg = &f->tsg[ch->tsgid]; | ||
3490 | } | ||
3491 | 3494 | ||
3492 | if (add) { | 3495 | if (add) { |
3493 | if (test_and_set_bit(chid, | 3496 | if (test_and_set_bit(chid, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 46cbfd8c..9e4d3c37 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -8077,6 +8077,7 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch) | |||
8077 | struct gk20a *g = ch->g; | 8077 | struct gk20a *g = ch->g; |
8078 | struct channel_gk20a *curr_ch; | 8078 | struct channel_gk20a *curr_ch; |
8079 | bool ret = false; | 8079 | bool ret = false; |
8080 | struct tsg_gk20a *tsg; | ||
8080 | 8081 | ||
8081 | curr_gr_ctx = gk20a_readl(g, gr_fecs_current_ctx_r()); | 8082 | curr_gr_ctx = gk20a_readl(g, gr_fecs_current_ctx_r()); |
8082 | 8083 | ||
@@ -8108,7 +8109,8 @@ bool gk20a_is_channel_ctx_resident(struct channel_gk20a *ch) | |||
8108 | ret = true; | 8109 | ret = true; |
8109 | } | 8110 | } |
8110 | 8111 | ||
8111 | if (gk20a_is_channel_marked_as_tsg(ch) && (ch->tsgid == curr_gr_tsgid)) { | 8112 | tsg = tsg_gk20a_from_ch(ch); |
8113 | if ((tsg != NULL) && (tsg->tsgid == curr_gr_tsgid)) { | ||
8112 | ret = true; | 8114 | ret = true; |
8113 | } | 8115 | } |
8114 | 8116 | ||