diff options
Diffstat (limited to 'drivers/gpu/nvgpu/gk20a')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 37 |
1 files changed, 31 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index afa665ab..4dec9e99 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -8588,17 +8588,23 @@ int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, | |||
8588 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); | 8588 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); |
8589 | u32 offset = | 8589 | u32 offset = |
8590 | gpc_stride * gpc + tpc_in_gpc_stride * tpc; | 8590 | gpc_stride * gpc + tpc_in_gpc_stride * tpc; |
8591 | u32 dbgr_status0 = 0, dbgr_control0 = 0; | ||
8592 | u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0; | ||
8593 | struct nvgpu_timeout timeout; | ||
8591 | 8594 | ||
8592 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, | 8595 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, |
8593 | "GPC%d TPC%d: locking down SM", gpc, tpc); | 8596 | "GPC%d TPC%d: locking down SM", gpc, tpc); |
8594 | 8597 | ||
8598 | nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g), | ||
8599 | NVGPU_TIMER_CPU_TIMER); | ||
8600 | |||
8595 | /* wait for the sm to lock down */ | 8601 | /* wait for the sm to lock down */ |
8596 | do { | 8602 | do { |
8597 | u32 global_esr = gk20a_readl(g, | 8603 | u32 global_esr = gk20a_readl(g, |
8598 | gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); | 8604 | gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); |
8599 | u32 warp_esr = gk20a_readl(g, | 8605 | u32 warp_esr = gk20a_readl(g, |
8600 | gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset); | 8606 | gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset); |
8601 | u32 dbgr_status0 = gk20a_readl(g, | 8607 | dbgr_status0 = gk20a_readl(g, |
8602 | gr_gpc0_tpc0_sm_dbgr_status0_r() + offset); | 8608 | gr_gpc0_tpc0_sm_dbgr_status0_r() + offset); |
8603 | 8609 | ||
8604 | warp_esr = g->ops.gr.mask_hww_warp_esr(warp_esr); | 8610 | warp_esr = g->ops.gr.mask_hww_warp_esr(warp_esr); |
@@ -8630,13 +8636,32 @@ int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, | |||
8630 | 8636 | ||
8631 | usleep_range(delay, delay * 2); | 8637 | usleep_range(delay, delay * 2); |
8632 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); | 8638 | delay = min_t(u32, delay << 1, GR_IDLE_CHECK_MAX); |
8633 | } while (!locked_down); | 8639 | } while (!nvgpu_timeout_expired(&timeout) |
8640 | || !tegra_platform_is_silicon()); | ||
8641 | |||
8642 | dbgr_control0 = gk20a_readl(g, | ||
8643 | gr_gpc0_tpc0_sm_dbgr_control0_r() + offset); | ||
8634 | 8644 | ||
8645 | /* 64 bit read */ | ||
8646 | warps_valid = (u64)gk20a_readl(g, gr_gpc0_tpc0_sm_warp_valid_mask_1_r() + offset) << 32; | ||
8647 | warps_valid |= gk20a_readl(g, gr_gpc0_tpc0_sm_warp_valid_mask_r() + offset); | ||
8648 | |||
8649 | /* 64 bit read */ | ||
8650 | warps_paused = (u64)gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_1_r() + offset) << 32; | ||
8651 | warps_paused |= gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r() + offset); | ||
8652 | |||
8653 | /* 64 bit read */ | ||
8654 | warps_trapped = (u64)gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_1_r() + offset) << 32; | ||
8655 | warps_trapped |= gk20a_readl(g, gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r() + offset); | ||
8656 | |||
8657 | gk20a_err(dev_from_gk20a(g), | ||
8658 | "GPC%d TPC%d: timed out while trying to lock down SM", gpc, tpc); | ||
8635 | gk20a_err(dev_from_gk20a(g), | 8659 | gk20a_err(dev_from_gk20a(g), |
8636 | "GPC%d TPC%d: timed out while trying to lock down SM", | 8660 | "STATUS0(0x%x)=0x%x CONTROL0=0x%x VALID_MASK=0x%llx PAUSE_MASK=0x%llx TRAP_MASK=0x%llx\n", |
8637 | gpc, tpc); | 8661 | gr_gpc0_tpc0_sm_dbgr_status0_r() + offset, dbgr_status0, dbgr_control0, |
8662 | warps_valid, warps_paused, warps_trapped); | ||
8638 | 8663 | ||
8639 | return -EAGAIN; | 8664 | return -ETIMEDOUT; |
8640 | } | 8665 | } |
8641 | 8666 | ||
8642 | void gk20a_suspend_single_sm(struct gk20a *g, | 8667 | void gk20a_suspend_single_sm(struct gk20a *g, |
@@ -8699,7 +8724,7 @@ void gk20a_suspend_all_sms(struct gk20a *g, | |||
8699 | gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0); | 8724 | gr_gpcs_tpcs_sm_dbgr_control0_r(), dbgr_control0); |
8700 | 8725 | ||
8701 | for (gpc = 0; gpc < gr->gpc_count; gpc++) { | 8726 | for (gpc = 0; gpc < gr->gpc_count; gpc++) { |
8702 | for (tpc = 0; tpc < gr->tpc_count; tpc++) { | 8727 | for (tpc = 0; tpc < gr_gk20a_get_tpc_count(gr, gpc); tpc++) { |
8703 | err = | 8728 | err = |
8704 | gk20a_gr_wait_for_sm_lock_down(g, gpc, tpc, | 8729 | gk20a_gr_wait_for_sm_lock_down(g, gpc, tpc, |
8705 | global_esr_mask, check_errors); | 8730 | global_esr_mask, check_errors); |